lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 20 Nov 2020 17:16:56 +0100
From:   Thierry Reding <>
To:     Nicolin Chen <>
Subject: Re: [PATCH] clk: tegra: Do not return 0 on failure

On Wed, Oct 28, 2020 at 05:48:20PM -0700, Nicolin Chen wrote:
> Return values from read_dt_param() will be either TRUE (1) or
> FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
> or an ERR code on failure.
> So this patch fixes the bug of returning 0 on failure.
> Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control")
> Cc: <>
> Signed-off-by: Nicolin Chen <>
> ---
>  drivers/clk/tegra/clk-dfll.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Mike, Stephen,

if you don't mind, I'll pick this up in the Tegra tree since there are a
few other Tegra clock patches on the list that may require coordination
inside the Tegra tree.


Download attachment "signature.asc" of type "application/pgp-signature" (834 bytes)

Powered by blists - more mailing lists