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Message-ID: <202011210218.eUYhiOps-lkp@intel.com>
Date: Sat, 21 Nov 2020 02:39:22 +0800
From: kernel test robot <lkp@...el.com>
To: Steen Hegelund <steen.hegelund@...rochip.com>,
Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>
Cc: kbuild-all@...ts.01.org, clang-built-linux@...glegroups.com,
Steen Hegelund <steen.hegelund@...rochip.com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Lars Povlsen <lars.povlsen@...rochip.com>,
Bjarni Jonasson <bjarni.jonasson@...rochip.com>,
Microsemi List <microsemi@...ts.bootlin.com>,
Microchip UNG Driver List <UNGLinuxDriver@...rochip.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 2/4] phy: Add ethernet serdes configuration option
Hi Steen,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/dt/next]
[also build test ERROR on linus/master robh/for-next linux/master 3cea11cd5e3b00d91caf0b4730194039b45c5891 v5.10-rc4 next-20201120]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Steen-Hegelund/Adding-the-Sparx5-Serdes-driver/20201120-230836
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git dt/next
config: powerpc64-randconfig-r015-20201120 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 3ded927cf80ac519f9f9c4664fef08787f7c537d)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install powerpc64 cross compiling tool for clang build
# apt-get install binutils-powerpc64-linux-gnu
# https://github.com/0day-ci/linux/commit/e184a313fca4f75b4f4f8abca27c8c2f1fb29540
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Steen-Hegelund/Adding-the-Sparx5-Serdes-driver/20201120-230836
git checkout e184a313fca4f75b4f4f8abca27c8c2f1fb29540
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=powerpc64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All errors (new ones prefixed by >>):
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:110:12: error: conflicting types for 'phy_write'
static int phy_write(struct phy *phy, u32 value, unsigned int reg)
^
include/linux/phy.h:987:19: note: previous definition is here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
>> drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:292:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:293:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:294:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:295:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:296:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:297:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:298:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:314:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, CM(priv->cfg.cm), DPHY_CM);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:315:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, CN(priv->cfg.cn), DPHY_CN);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:316:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, CO(priv->cfg.co), DPHY_CO);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:333:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, 0x00, DPHY_LOCK_BYP);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:334:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, 0x01, priv->devdata->reg_tx_rcal);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:335:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, 0x00, priv->devdata->reg_auto_pd_en);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:336:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, 0x02, priv->devdata->reg_rxlprp);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:337:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, 0x02, priv->devdata->reg_rxcdrp);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:338:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, 0x25, DPHY_TST);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
^
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:361:12: error: incompatible pointer types passing 'struct phy *' to parameter of type 'struct phy_device *' [-Werror,-Wincompatible-pointer-types]
phy_write(phy, PWR_OFF, DPHY_PD_PLL);
^~~
include/linux/phy.h:987:48: note: passing argument to parameter 'phydev' here
static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
vim +292 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
f4c8116e294b12c Guido Günther 2019-06-20 109
f4c8116e294b12c Guido Günther 2019-06-20 @110 static int phy_write(struct phy *phy, u32 value, unsigned int reg)
f4c8116e294b12c Guido Günther 2019-06-20 111 {
f4c8116e294b12c Guido Günther 2019-06-20 112 struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
f4c8116e294b12c Guido Günther 2019-06-20 113 int ret;
f4c8116e294b12c Guido Günther 2019-06-20 114
f4c8116e294b12c Guido Günther 2019-06-20 115 ret = regmap_write(priv->regmap, reg, value);
f4c8116e294b12c Guido Günther 2019-06-20 116 if (ret < 0)
f4c8116e294b12c Guido Günther 2019-06-20 117 dev_err(&phy->dev, "Failed to write DPHY reg %d: %d\n", reg,
f4c8116e294b12c Guido Günther 2019-06-20 118 ret);
f4c8116e294b12c Guido Günther 2019-06-20 119 return ret;
f4c8116e294b12c Guido Günther 2019-06-20 120 }
f4c8116e294b12c Guido Günther 2019-06-20 121
f4c8116e294b12c Guido Günther 2019-06-20 122 /*
f4c8116e294b12c Guido Günther 2019-06-20 123 * Find a ratio close to the desired one using continued fraction
f4c8116e294b12c Guido Günther 2019-06-20 124 * approximation ending either at exact match or maximum allowed
f4c8116e294b12c Guido Günther 2019-06-20 125 * nominator, denominator.
f4c8116e294b12c Guido Günther 2019-06-20 126 */
f4c8116e294b12c Guido Günther 2019-06-20 127 static void get_best_ratio(u32 *pnum, u32 *pdenom, u32 max_n, u32 max_d)
f4c8116e294b12c Guido Günther 2019-06-20 128 {
f4c8116e294b12c Guido Günther 2019-06-20 129 u32 a = *pnum;
f4c8116e294b12c Guido Günther 2019-06-20 130 u32 b = *pdenom;
f4c8116e294b12c Guido Günther 2019-06-20 131 u32 c;
f4c8116e294b12c Guido Günther 2019-06-20 132 u32 n[] = {0, 1};
f4c8116e294b12c Guido Günther 2019-06-20 133 u32 d[] = {1, 0};
f4c8116e294b12c Guido Günther 2019-06-20 134 u32 whole;
f4c8116e294b12c Guido Günther 2019-06-20 135 unsigned int i = 1;
f4c8116e294b12c Guido Günther 2019-06-20 136
f4c8116e294b12c Guido Günther 2019-06-20 137 while (b) {
f4c8116e294b12c Guido Günther 2019-06-20 138 i ^= 1;
f4c8116e294b12c Guido Günther 2019-06-20 139 whole = a / b;
f4c8116e294b12c Guido Günther 2019-06-20 140 n[i] += (n[i ^ 1] * whole);
f4c8116e294b12c Guido Günther 2019-06-20 141 d[i] += (d[i ^ 1] * whole);
f4c8116e294b12c Guido Günther 2019-06-20 142 if ((n[i] > max_n) || (d[i] > max_d)) {
f4c8116e294b12c Guido Günther 2019-06-20 143 i ^= 1;
f4c8116e294b12c Guido Günther 2019-06-20 144 break;
f4c8116e294b12c Guido Günther 2019-06-20 145 }
f4c8116e294b12c Guido Günther 2019-06-20 146 c = a - (b * whole);
f4c8116e294b12c Guido Günther 2019-06-20 147 a = b;
f4c8116e294b12c Guido Günther 2019-06-20 148 b = c;
f4c8116e294b12c Guido Günther 2019-06-20 149 }
f4c8116e294b12c Guido Günther 2019-06-20 150 *pnum = n[i];
f4c8116e294b12c Guido Günther 2019-06-20 151 *pdenom = d[i];
f4c8116e294b12c Guido Günther 2019-06-20 152 }
f4c8116e294b12c Guido Günther 2019-06-20 153
f4c8116e294b12c Guido Günther 2019-06-20 154 static int mixel_dphy_config_from_opts(struct phy *phy,
f4c8116e294b12c Guido Günther 2019-06-20 155 struct phy_configure_opts_mipi_dphy *dphy_opts,
f4c8116e294b12c Guido Günther 2019-06-20 156 struct mixel_dphy_cfg *cfg)
f4c8116e294b12c Guido Günther 2019-06-20 157 {
f4c8116e294b12c Guido Günther 2019-06-20 158 struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent);
f4c8116e294b12c Guido Günther 2019-06-20 159 unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk);
f4c8116e294b12c Guido Günther 2019-06-20 160 u32 lp_t, numerator, denominator;
f4c8116e294b12c Guido Günther 2019-06-20 161 unsigned long long tmp;
f4c8116e294b12c Guido Günther 2019-06-20 162 u32 n;
f4c8116e294b12c Guido Günther 2019-06-20 163 int i;
f4c8116e294b12c Guido Günther 2019-06-20 164
f4c8116e294b12c Guido Günther 2019-06-20 165 if (dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED ||
f4c8116e294b12c Guido Günther 2019-06-20 166 dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED)
f4c8116e294b12c Guido Günther 2019-06-20 167 return -EINVAL;
f4c8116e294b12c Guido Günther 2019-06-20 168
f4c8116e294b12c Guido Günther 2019-06-20 169 numerator = dphy_opts->hs_clk_rate;
f4c8116e294b12c Guido Günther 2019-06-20 170 denominator = ref_clk;
f4c8116e294b12c Guido Günther 2019-06-20 171 get_best_ratio(&numerator, &denominator, 255, 256);
f4c8116e294b12c Guido Günther 2019-06-20 172 if (!numerator || !denominator) {
f4c8116e294b12c Guido Günther 2019-06-20 173 dev_err(&phy->dev, "Invalid %d/%d for %ld/%ld\n",
f4c8116e294b12c Guido Günther 2019-06-20 174 numerator, denominator,
f4c8116e294b12c Guido Günther 2019-06-20 175 dphy_opts->hs_clk_rate, ref_clk);
f4c8116e294b12c Guido Günther 2019-06-20 176 return -EINVAL;
f4c8116e294b12c Guido Günther 2019-06-20 177 }
f4c8116e294b12c Guido Günther 2019-06-20 178
f4c8116e294b12c Guido Günther 2019-06-20 179 while ((numerator < 16) && (denominator <= 128)) {
f4c8116e294b12c Guido Günther 2019-06-20 180 numerator <<= 1;
f4c8116e294b12c Guido Günther 2019-06-20 181 denominator <<= 1;
f4c8116e294b12c Guido Günther 2019-06-20 182 }
f4c8116e294b12c Guido Günther 2019-06-20 183 /*
f4c8116e294b12c Guido Günther 2019-06-20 184 * CM ranges between 16 and 255
f4c8116e294b12c Guido Günther 2019-06-20 185 * CN ranges between 1 and 32
f4c8116e294b12c Guido Günther 2019-06-20 186 * CO is power of 2: 1, 2, 4, 8
f4c8116e294b12c Guido Günther 2019-06-20 187 */
f4c8116e294b12c Guido Günther 2019-06-20 188 i = __ffs(denominator);
f4c8116e294b12c Guido Günther 2019-06-20 189 if (i > 3)
f4c8116e294b12c Guido Günther 2019-06-20 190 i = 3;
f4c8116e294b12c Guido Günther 2019-06-20 191 cfg->cn = denominator >> i;
f4c8116e294b12c Guido Günther 2019-06-20 192 cfg->co = 1 << i;
f4c8116e294b12c Guido Günther 2019-06-20 193 cfg->cm = numerator;
f4c8116e294b12c Guido Günther 2019-06-20 194
f4c8116e294b12c Guido Günther 2019-06-20 195 if (cfg->cm < 16 || cfg->cm > 255 ||
f4c8116e294b12c Guido Günther 2019-06-20 196 cfg->cn < 1 || cfg->cn > 32 ||
f4c8116e294b12c Guido Günther 2019-06-20 197 cfg->co < 1 || cfg->co > 8) {
f4c8116e294b12c Guido Günther 2019-06-20 198 dev_err(&phy->dev, "Invalid CM/CN/CO values: %u/%u/%u\n",
f4c8116e294b12c Guido Günther 2019-06-20 199 cfg->cm, cfg->cn, cfg->co);
f4c8116e294b12c Guido Günther 2019-06-20 200 dev_err(&phy->dev, "for hs_clk/ref_clk=%ld/%ld ~ %d/%d\n",
f4c8116e294b12c Guido Günther 2019-06-20 201 dphy_opts->hs_clk_rate, ref_clk,
f4c8116e294b12c Guido Günther 2019-06-20 202 numerator, denominator);
f4c8116e294b12c Guido Günther 2019-06-20 203 return -EINVAL;
f4c8116e294b12c Guido Günther 2019-06-20 204 }
f4c8116e294b12c Guido Günther 2019-06-20 205
f4c8116e294b12c Guido Günther 2019-06-20 206 dev_dbg(&phy->dev, "hs_clk/ref_clk=%ld/%ld ~ %d/%d\n",
f4c8116e294b12c Guido Günther 2019-06-20 207 dphy_opts->hs_clk_rate, ref_clk, numerator, denominator);
f4c8116e294b12c Guido Günther 2019-06-20 208
f4c8116e294b12c Guido Günther 2019-06-20 209 /* LP clock period */
f4c8116e294b12c Guido Günther 2019-06-20 210 tmp = 1000000000000LL;
f4c8116e294b12c Guido Günther 2019-06-20 211 do_div(tmp, dphy_opts->lp_clk_rate); /* ps */
f4c8116e294b12c Guido Günther 2019-06-20 212 if (tmp > ULONG_MAX)
f4c8116e294b12c Guido Günther 2019-06-20 213 return -EINVAL;
f4c8116e294b12c Guido Günther 2019-06-20 214
f4c8116e294b12c Guido Günther 2019-06-20 215 lp_t = tmp;
f4c8116e294b12c Guido Günther 2019-06-20 216 dev_dbg(&phy->dev, "LP clock %lu, period: %u ps\n",
f4c8116e294b12c Guido Günther 2019-06-20 217 dphy_opts->lp_clk_rate, lp_t);
f4c8116e294b12c Guido Günther 2019-06-20 218
f4c8116e294b12c Guido Günther 2019-06-20 219 /* hs_prepare: in lp clock periods */
f4c8116e294b12c Guido Günther 2019-06-20 220 if (2 * dphy_opts->hs_prepare > 5 * lp_t) {
f4c8116e294b12c Guido Günther 2019-06-20 221 dev_err(&phy->dev,
f4c8116e294b12c Guido Günther 2019-06-20 222 "hs_prepare (%u) > 2.5 * lp clock period (%u)\n",
f4c8116e294b12c Guido Günther 2019-06-20 223 dphy_opts->hs_prepare, lp_t);
f4c8116e294b12c Guido Günther 2019-06-20 224 return -EINVAL;
f4c8116e294b12c Guido Günther 2019-06-20 225 }
f4c8116e294b12c Guido Günther 2019-06-20 226 /* 00: lp_t, 01: 1.5 * lp_t, 10: 2 * lp_t, 11: 2.5 * lp_t */
f4c8116e294b12c Guido Günther 2019-06-20 227 if (dphy_opts->hs_prepare < lp_t) {
f4c8116e294b12c Guido Günther 2019-06-20 228 n = 0;
f4c8116e294b12c Guido Günther 2019-06-20 229 } else {
f4c8116e294b12c Guido Günther 2019-06-20 230 tmp = 2 * (dphy_opts->hs_prepare - lp_t);
f4c8116e294b12c Guido Günther 2019-06-20 231 do_div(tmp, lp_t);
f4c8116e294b12c Guido Günther 2019-06-20 232 n = tmp;
f4c8116e294b12c Guido Günther 2019-06-20 233 }
f4c8116e294b12c Guido Günther 2019-06-20 234 cfg->m_prg_hs_prepare = n;
f4c8116e294b12c Guido Günther 2019-06-20 235
f4c8116e294b12c Guido Günther 2019-06-20 236 /* clk_prepare: in lp clock periods */
f4c8116e294b12c Guido Günther 2019-06-20 237 if (2 * dphy_opts->clk_prepare > 3 * lp_t) {
f4c8116e294b12c Guido Günther 2019-06-20 238 dev_err(&phy->dev,
f4c8116e294b12c Guido Günther 2019-06-20 239 "clk_prepare (%u) > 1.5 * lp clock period (%u)\n",
f4c8116e294b12c Guido Günther 2019-06-20 240 dphy_opts->clk_prepare, lp_t);
f4c8116e294b12c Guido Günther 2019-06-20 241 return -EINVAL;
f4c8116e294b12c Guido Günther 2019-06-20 242 }
f4c8116e294b12c Guido Günther 2019-06-20 243 /* 00: lp_t, 01: 1.5 * lp_t */
f4c8116e294b12c Guido Günther 2019-06-20 244 cfg->mc_prg_hs_prepare = dphy_opts->clk_prepare > lp_t ? 1 : 0;
f4c8116e294b12c Guido Günther 2019-06-20 245
f4c8116e294b12c Guido Günther 2019-06-20 246 /* hs_zero: formula from NXP BSP */
f4c8116e294b12c Guido Günther 2019-06-20 247 n = (144 * (dphy_opts->hs_clk_rate / 1000000) - 47500) / 10000;
f4c8116e294b12c Guido Günther 2019-06-20 248 cfg->m_prg_hs_zero = n < 1 ? 1 : n;
f4c8116e294b12c Guido Günther 2019-06-20 249
f4c8116e294b12c Guido Günther 2019-06-20 250 /* clk_zero: formula from NXP BSP */
f4c8116e294b12c Guido Günther 2019-06-20 251 n = (34 * (dphy_opts->hs_clk_rate / 1000000) - 2500) / 1000;
f4c8116e294b12c Guido Günther 2019-06-20 252 cfg->mc_prg_hs_zero = n < 1 ? 1 : n;
f4c8116e294b12c Guido Günther 2019-06-20 253
f4c8116e294b12c Guido Günther 2019-06-20 254 /* clk_trail, hs_trail: formula from NXP BSP */
f4c8116e294b12c Guido Günther 2019-06-20 255 n = (103 * (dphy_opts->hs_clk_rate / 1000000) + 10000) / 10000;
f4c8116e294b12c Guido Günther 2019-06-20 256 if (n > 15)
f4c8116e294b12c Guido Günther 2019-06-20 257 n = 15;
f4c8116e294b12c Guido Günther 2019-06-20 258 if (n < 1)
f4c8116e294b12c Guido Günther 2019-06-20 259 n = 1;
f4c8116e294b12c Guido Günther 2019-06-20 260 cfg->m_prg_hs_trail = n;
f4c8116e294b12c Guido Günther 2019-06-20 261 cfg->mc_prg_hs_trail = n;
f4c8116e294b12c Guido Günther 2019-06-20 262
f4c8116e294b12c Guido Günther 2019-06-20 263 /* rxhs_settle: formula from NXP BSP */
f4c8116e294b12c Guido Günther 2019-06-20 264 if (dphy_opts->hs_clk_rate < MBPS(80))
f4c8116e294b12c Guido Günther 2019-06-20 265 cfg->rxhs_settle = 0x0d;
f4c8116e294b12c Guido Günther 2019-06-20 266 else if (dphy_opts->hs_clk_rate < MBPS(90))
f4c8116e294b12c Guido Günther 2019-06-20 267 cfg->rxhs_settle = 0x0c;
f4c8116e294b12c Guido Günther 2019-06-20 268 else if (dphy_opts->hs_clk_rate < MBPS(125))
f4c8116e294b12c Guido Günther 2019-06-20 269 cfg->rxhs_settle = 0x0b;
f4c8116e294b12c Guido Günther 2019-06-20 270 else if (dphy_opts->hs_clk_rate < MBPS(150))
f4c8116e294b12c Guido Günther 2019-06-20 271 cfg->rxhs_settle = 0x0a;
f4c8116e294b12c Guido Günther 2019-06-20 272 else if (dphy_opts->hs_clk_rate < MBPS(225))
f4c8116e294b12c Guido Günther 2019-06-20 273 cfg->rxhs_settle = 0x09;
f4c8116e294b12c Guido Günther 2019-06-20 274 else if (dphy_opts->hs_clk_rate < MBPS(500))
f4c8116e294b12c Guido Günther 2019-06-20 275 cfg->rxhs_settle = 0x08;
f4c8116e294b12c Guido Günther 2019-06-20 276 else
f4c8116e294b12c Guido Günther 2019-06-20 277 cfg->rxhs_settle = 0x07;
f4c8116e294b12c Guido Günther 2019-06-20 278
f4c8116e294b12c Guido Günther 2019-06-20 279 dev_dbg(&phy->dev, "phy_config: %u %u %u %u %u %u %u\n",
f4c8116e294b12c Guido Günther 2019-06-20 280 cfg->m_prg_hs_prepare, cfg->mc_prg_hs_prepare,
f4c8116e294b12c Guido Günther 2019-06-20 281 cfg->m_prg_hs_zero, cfg->mc_prg_hs_zero,
f4c8116e294b12c Guido Günther 2019-06-20 282 cfg->m_prg_hs_trail, cfg->mc_prg_hs_trail,
f4c8116e294b12c Guido Günther 2019-06-20 283 cfg->rxhs_settle);
f4c8116e294b12c Guido Günther 2019-06-20 284
f4c8116e294b12c Guido Günther 2019-06-20 285 return 0;
f4c8116e294b12c Guido Günther 2019-06-20 286 }
f4c8116e294b12c Guido Günther 2019-06-20 287
f4c8116e294b12c Guido Günther 2019-06-20 288 static void mixel_phy_set_hs_timings(struct phy *phy)
f4c8116e294b12c Guido Günther 2019-06-20 289 {
f4c8116e294b12c Guido Günther 2019-06-20 290 struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
f4c8116e294b12c Guido Günther 2019-06-20 291
f4c8116e294b12c Guido Günther 2019-06-20 @292 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE);
f4c8116e294b12c Guido Günther 2019-06-20 293 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE);
f4c8116e294b12c Guido Günther 2019-06-20 294 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO);
f4c8116e294b12c Guido Günther 2019-06-20 295 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO);
f4c8116e294b12c Guido Günther 2019-06-20 296 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL);
f4c8116e294b12c Guido Günther 2019-06-20 297 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL);
f4c8116e294b12c Guido Günther 2019-06-20 298 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle);
f4c8116e294b12c Guido Günther 2019-06-20 299 }
f4c8116e294b12c Guido Günther 2019-06-20 300
---
0-DAY CI Kernel Test Service, Intel Corporation
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