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Date:   Thu, 19 Nov 2020 22:24:40 -0600
From:   Bjorn Andersson <bjorn.andersson@...aro.org>
To:     Souradeep Chowdhury <schowdhu@...eaurora.org>
Cc:     devicetree@...r.kernel.org, Andy Gross <agross@...nel.org>,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        Rajendra Nayak <rnayak@...eaurora.org>
Subject: Re: [PATCH V1 3/3] arm64: dts: qcom: sm8150: Add LLC support for
 sm8150

On Wed 30 Sep 03:14 CDT 2020, Souradeep Chowdhury wrote:

> Add LLCC system cache controller entry for sm8150 to support sm8150
> for LLCC.
> 

Thank you for your patches Souradeep, unfortunately there where some
indentation issues that you would have seen if you ran
./scripts/checkpatch.pl --strict.

I fixed these issues up and applied the patches towards v5.11.

Thank you,
Bjorn

> Signed-off-by: Souradeep Chowdhury <schowdhu@...eaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index f0a872e02686..71037a1bb217 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -490,7 +490,14 @@
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
>  
> -		ufs_mem_hc: ufshc@...4000 {
> +	        system-cache-controller@...0000 {
> +                        compatible = "qcom,sm8150-llcc";
> +                        reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
> +                        reg-names = "llcc_base", "llcc_broadcast_base";
> +                        interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> +                 };
> +
> +        	ufs_mem_hc: ufshc@...4000 {
>  			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
>  				     "jedec,ufs-2.0";
>  			reg = <0 0x01d84000 0 0x2500>;
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
> 

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