linux-kernel - Re: [PATCH v4 24/25] arm64: Add TRFCR

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Message-ID: <43d9f4ac-df91-1cc4-ea4b-518f3433a915@arm.com>
Date:   Fri, 20 Nov 2020 10:03:37 +0000
From:   Suzuki K Poulose <suzuki.poulose@....com>
To:     Catalin Marinas <catalin.marinas@....com>
Cc:     linux-arm-kernel@...ts.infradead.org, mathieu.poirier@...aro.org,
        mike.leach@...aro.org, linux-kernel@...r.kernel.org,
        anshuman.khandual@....com, jonathan.zhouwen@...wei.com,
        coresight@...ts.linaro.org, Will Deacon <will@...nel.org>
Subject: Re: [PATCH v4 24/25] arm64: Add TRFCR_ELx definitions

On 11/19/20 5:18 PM, Catalin Marinas wrote:
> On Thu, Nov 19, 2020 at 04:45:46PM +0000, Suzuki K Poulose wrote:
>> @@ -988,6 +991,14 @@
>>   /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
>>   #define SYS_MPIDR_SAFE_VAL	(BIT(31))
>>   
>> +#define TRFCR_ELx_TS_SHIFT		5
>> +#define TRFCR_ELx_TS_VIRTUAL		((0x1) << TRFCR_ELx_TS_SHIFT)
>> +#define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2) << TRFCR_ELx_TS_SHIFT)
>> +#define TRFCR_ELx_TS_PHYSICAL		((0x3) << TRFCR_ELx_TS_SHIFT)
> 
> For consistency, I'd use 0x1UL etc. in case the shift goes beyond 32
> (not the case here though).

Agreed, will fix it.

> 
> Otherwise:
> 
> Acked-by: Catalin Marinas <catalin.marinas@....com>

Thanks
Suzuki