lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20201120102042.25caeib3iiuxkogt@bogus>
Date:   Fri, 20 Nov 2020 10:20:42 +0000
From:   Sudeep Holla <sudeep.holla@....com>
To:     Marc Zyngier <maz@...nel.org>
Cc:     Neeraj Upadhyay <neeraju@...eaurora.org>, mark.rutland@....com,
        suzuki.poulose@....com, ionela.voinescu@....com,
        MSM <linux-arm-msm@...r.kernel.org>,
        lkml <linux-kernel@...r.kernel.org>, catalin.marinas@....com,
        Will Deacon <will@...nel.org>, valentin.schneider@....com,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: AMU extension v1 support for cortex A76, A77, A78 CPUs

On Fri, Nov 20, 2020 at 08:56:31AM +0000, Marc Zyngier wrote:
> On 2020-11-20 04:30, Neeraj Upadhyay wrote:
> > Hi,
> >
> > For ARM cortex A76, A77, A78 cores (which as per TRM, support AMU)
> > AA64PFR0[47:44] field is not set, and AMU does not get enabled for
> > them.
> > Can you please provide support for these CPUs in cpufeature.c?
>
> If that was the case, that'd be an erratum, and it would need to be
> documented as such. It could also be that this is an optional feature
> for these cores (though the TRM doesn't suggest that).
>
> Can someone at ARM confirm what is the expected behaviour of these CPUs?

IIRC discussion with Ionela long back, we intentionally decided not to
support IMPDEF(pre 8.4 non-architected so called AMUs) on the CPUs listed
in $subject.

--
Regards,
Sudeep

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ