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Message-ID: <20201120103612.GJ2925@vkoul-mobl>
Date: Fri, 20 Nov 2020 16:06:12 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Marek Szyprowski <m.szyprowski@...sung.com>
Cc: linux-samsung-soc@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Jaehoon Chung <jh80.chung@...sung.com>,
Jingoo Han <jingoohan1@...il.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Kishon Vijay Abraham I <kishon@...com>,
Rob Herring <robh@...nel.org>,
Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>
Subject: Re: [PATCH v4 4/5 REBASED RESEND] phy: samsung: phy-exynos-pcie:
rework driver to support Exynos5433 PCIe PHY
On 20-11-20, 11:26, Marek Szyprowski wrote:
> From: Jaehoon Chung <jh80.chung@...sung.com>
>
> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
> dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
> variant found in the Exynos5433 SoCs.
Applied, thanks
My scripts found a typo, have applied fix for that as well
From: Vinod Koul <vkoul@...nel.org>
Date: Fri, 20 Nov 2020 16:04:01 +0530
Subject: [PATCH] phy: samsung: phy-exynos-pcie: fix typo 'tunning'
Fix the typo s/tunning/tuning
Fixes: 496db029142f ("phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY")
Signed-off-by: Vinod Koul <vkoul@...nel.org>
---
drivers/phy/samsung/phy-exynos-pcie.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
index d91de323dd0e..578cfe07d07a 100644
--- a/drivers/phy/samsung/phy-exynos-pcie.c
+++ b/drivers/phy/samsung/phy-exynos-pcie.c
@@ -69,7 +69,7 @@ static int exynos5433_pcie_phy_init(struct phy *phy)
exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20));
exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b));
- /* jitter tunning */
+ /* jitter tuning */
exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4));
exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7));
exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21));
--
~Vinod
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