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Message-ID: <CAAOTY_9SGD4jmWQW-LvWjzJ4z0itupw9qei=JhXTmBWAia-xOQ@mail.gmail.com>
Date: Fri, 20 Nov 2020 22:41:15 +0800
From: Chun-Kuang Hu <chunkuang.hu@...nel.org>
To: Daoyuan Huang <daoyuan.huang@...iatek.com>
Cc: Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Hans Verkuil <hverkuil-cisco@...all.nl>,
Jernej Skrabec <jernej.skrabec@...l.net>,
Maoguang Meng <maoguang.meng@...iatek.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
menghui.lin@...iatek.com,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Nicolas Boichat <drinkcat@...omium.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Ping-Hsun Wu <ping-hsun.wu@...iatek.com>,
linux-media@...r.kernel.org, DTML <devicetree@...r.kernel.org>,
Sj Huang (黃信璋) <sj.huang@...iatek.com>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>, pihsun@...omium.org,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
randy.wu@...iatek.com,
srv_heupstream <srv_heupstream@...iatek.com>,
acourbot@...omium.org, linux-kernel <linux-kernel@...r.kernel.org>,
Tomasz Figa <tfiga@...omium.org>, ben.lok@...iatek.com,
moudy.ho@...iatek.com, Rob Landley <rob@...dley.net>
Subject: Re: [PATCH v4 1/4] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
Hi, Daoyuan:
Daoyuan Huang <daoyuan.huang@...iatek.com> 於 2020年11月20日 週五 上午10:41寫道：
>
> From: daoyuan huang <daoyuan.huang@...iatek.com>
>
> This patch adds DT binding document for Media Data Path 3 (MDP3)
> a unit in multimedia system used for scaling and color format convert.
>
> Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@...iatek.com>
> Signed-off-by: daoyuan huang <daoyuan.huang@...iatek.com>
> ---
> .../bindings/media/mediatek,mt8183-mdp3.txt | 208 ++++++++++++++++++
> 1 file changed, 208 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8183-mdp3.txt
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8183-mdp3.txt b/Documentation/devicetree/bindings/media/mediatek,mt8183-mdp3.txt
> new file mode 100644
> index 000000000000..d4db908b8b53
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mt8183-mdp3.txt
> @@ -0,0 +1,208 @@
> +* Mediatek Media Data Path 3
> +
> +Media Data Path 3 (MDP3) is used for scaling and color space conversion.
> +
> +Required properties (controller node):
> +- compatible: "mediatek,mt8183-mdp3"
> +- mediatek,scp: the node of system control processor (SCP), using the
> + remoteproc & rpmsg framework, see
> + Documentation/devicetree/bindings/remoteproc/mtk,scp.txt for details.
> +- mediatek,mmsys: the node of mux(multiplexer) controller for HW connections.
> +- mediatek,mm-mutex: the node of sof(start of frame) signal controller.
> +- mediatek,mailbox-gce: the node of global command engine (GCE), used to
> + read/write registers with critical time limitation, see
> + Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
> +- mboxes: mailbox number used to communicate with GCE.
> +- gce-subsys: sub-system id corresponding to the register address.
This is already defined in mediatek,gce-client-reg, so remove this.
> +- gce-event-names: in use event name list, used to correspond to event IDs.
> +- gce-events: in use event IDs list, all IDs are defined in
> + 'dt-bindings/gce/mt8183-gce.h'.
> +
> +Required properties (all function blocks, child node):
> +- compatible: Should be one of
> + "mediatek,mt8183-mdp-rdma" - read DMA
> + "mediatek,mt8183-mdp-rsz" - resizer
> + "mediatek,mt8183-mdp-wdma" - write DMA
> + "mediatek,mt8183-mdp-wrot" - write DMA with rotation
> + "mediatek,mt8183-mdp-ccorr" - color correction with 3X3 matrix
> +- reg: Physical base address and length of the function block register space.
> +- clocks: device clocks, see
> + Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> +- power-domains: A phandle to the power domain, see
> + Documentation/devicetree/bindings/power/power_domain.txt for details.
> +- mediatek,mdp-id: HW index to distinguish same functionality modules.
> +
> +Required properties (DMA function blocks, child node):
> +- compatible: Should be one of
> + "mediatek,mt8183-mdp-rdma"
> + "mediatek,mt8183-mdp-wdma"
> + "mediatek,mt8183-mdp-wrot"
> +- mdp-comps(wdma & wrot only):
> + "mediatek,mt8183-mdp-path" - MDP output path selection, create a
> + component for path connectedness of HW
> + pipe control; Align with mdp_comp_of_ids[]
> + in mtk-mdp3-comp.c.
> +- mdp-comp-ids(wdma & wrot only): Index of the output paths, the number aligns
> + with mdp_comp_matches[] in mtk-mdp3-comp.c.
> +- iommus: should point to the respective IOMMU block with master port as
> + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for
> + details.
> +- mediatek,larb: Must contain the local arbiters in the current Socs, see
> + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt for
> + details.
> +
> +Required properties (input path selection node):
> +- compatible:
> + "mediatek,mt8183-mmsys" - For MDP input/output source selection.
mmsys is defined in mediatek,mmsys.txt [1], so move this there.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt?h=v5.10-rc4
> +- mdp-comps:
> + "mediatek,mt8183-mdp-dl" - MDP direct link input path selection,
> + create a component for path connectedness
> + of HW pipe control; Align with
> + mdp_comp_of_ids[] in mtk-mdp3-comp.c.
> +- mdp-comp-ids: Index of the input paths, the number aligns with
> + mdp_comp_matches[] in mtk-mdp3-comp.c.
> +- reg: Physical base address and length of the function block register space.
> +- clocks: device clocks, see
> + Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> +
> +Required properties (ISP PASS2 (DIP) module path selection node):
> +- compatible:
> + "mediatek,mt8183-imgsys" - For ISP PASS2 (DIP) modules frame sync
> + control with MDP.
imgsys is defined in mediatek,imgsys.txt [2], so move this there.
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt?h=v5.10-rc4
> +- mdp-comps:
> + "mediatek,mt8183-mdp-imgi" - Input DMA of ISP PASS2 (DIP) module for
> + raw image input.
> + "mediatek,mt8183-mdp-exto" - Output DMA of ISP PASS2 (DIP) module for
> + yuv image output.
> +- mdp-comp-ids: Index of the modules, the number aligns with mdp_comp_matches[]
> + in mtk-mdp3-comp.c.
> +- reg: Physical base address and length of the function block register space.
> +- mediatek,mdp-id: HW index to distinguish same functionality modules.
> +
> +Example:
> + mmsys: syscon@...00000 {
> + compatible = "mediatek,mt8183-mmsys", "syscon";
> + mdp-comps = "mediatek,mt8183-mdp-dl",
> + "mediatek,mt8183-mdp-dl";
> + mdp-comp-ids = <0 1>;
> + reg = <0 0x14000000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> + #clock-cells = <1>;
> + clocks = <&mmsys CLK_MM_MDP_DL_TXCK>,
> + <&mmsys CLK_MM_MDP_DL_RX>,
> + <&mmsys CLK_MM_IPU_DL_TXCK>,
> + <&mmsys CLK_MM_IPU_DL_RX>;
> + };
> +
> + mdp_rdma0: mdp-rdma0@...01000 {
> + compatible = "mediatek,mt8183-mdp-rdma",
> + "mediatek,mt8183-mdp3";
> + mediatek,scp = <&scp>;
> + mediatek,mdp-id = <0>;
> + reg = <0 0x14001000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> + <&mmsys CLK_MM_MDP_RSZ1>;
Why place CLK_MM_MDP_RSZ1 in mdp_rdma0 device?
> + iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> + mediatek,larb = <&larb0>;
> + mediatek,mmsys = <&mmsys>;
> + mediatek,mm-mutex = <&mutex>;
> + mediatek,imgsys = <&imgsys>;
> + mediatek,mailbox-gce = <&gce>;
> + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
> + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
> + <&gce 0x14010000 SUBSYS_1401XXXX>,
> + <&gce 0x14020000 SUBSYS_1402XXXX>,
> + <&gce 0x15020000 SUBSYS_1502XXXX>;
> + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
> + <CMDQ_EVENT_MDP_RDMA0_EOF>,
> + <CMDQ_EVENT_MDP_RSZ0_SOF>,
mdp_rsz0 send CMDQ_EVENT_MDP_RSZ0_SOF to gce, so move
CMDQ_EVENT_MDP_RSZ0_SOF to mdp_rsz0.
> + <CMDQ_EVENT_MDP_RSZ1_SOF>,
> + <CMDQ_EVENT_MDP_TDSHP_SOF>,
> + <CMDQ_EVENT_MDP_WROT0_SOF>,
> + <CMDQ_EVENT_MDP_WROT0_EOF>,
> + <CMDQ_EVENT_MDP_WDMA0_SOF>,
> + <CMDQ_EVENT_MDP_WDMA0_EOF>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
> + <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
> + <CMDQ_EVENT_WPE_A_DONE>,
warp send CMDQ_EVENT_WPE_A_DONE to gce, so move CMDQ_EVENT_WPE_A_DONE
to warp device.
Regards,
Chun-Kuang.
> + <CMDQ_EVENT_SPE_B_DONE>;
> + };
> +
> + mdp_rsz0: mdp-rsz0@...03000 {
> + compatible = "mediatek,mt8183-mdp-rsz";
> + mediatek,mdp-id = <0>;
> + reg = <0 0x14003000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> + };
> +
> + mdp_rsz1: mdp-rsz1@...04000 {
> + compatible = "mediatek,mt8183-mdp-rsz";
> + mediatek,mdp-id = <1>;
> + reg = <0 0x14004000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> + };
> +
> + mdp_wrot0: mdp-wrot0@...05000 {
> + compatible = "mediatek,mt8183-mdp-wrot";
> + mediatek,mdp-id = <0>;
> + mdp-comps = "mediatek,mt8183-mdp-path";
> + mdp-comp-ids = <0>;
> + reg = <0 0x14005000 0 0x1000>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WROT0>;
> + iommus = <&iommu M4U_PORT_MDP_WROT0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + mdp_wdma: mdp-wdma@...06000 {
> + compatible = "mediatek,mt8183-mdp-wdma";
> + mediatek,mdp-id = <0>;
> + mdp-comps = "mediatek,mt8183-mdp-path";
> + mdp-comp-ids = <1>;
> + reg = <0 0x14006000 0 0x1000>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WDMA0>;
> + iommus = <&iommu M4U_PORT_MDP_WDMA0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + mdp_ccorr: mdp-ccorr@...1c000 {
> + compatible = "mediatek,mt8183-mdp-ccorr";
> + mediatek,mdp-id = <0>;
> + reg = <0 0x1401c000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> + };
> +
> + imgsys: syscon@...20000 {
> + compatible = "mediatek,mt8183-imgsys", "syscon";
> + mediatek,mdp-id = <0>;
> + mdp-comps = "mediatek,mt8183-mdp-imgi",
> + "mediatek,mt8183-mdp-exto";
> + mdp-comp-ids = <0 1>;
> + reg = <0 0x15020000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1502XXXX 0 0x1000>;
> + #clock-cells = <1>;
> + };
> --
> 2.18.0
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