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Message-ID: <1605838955.31607.43.camel@mhfsdcap03>
Date: Fri, 20 Nov 2020 10:22:35 +0800
From: Chunfeng Yun <chunfeng.yun@...iatek.com>
To: Chun-Kuang Hu <chunkuang.hu@...nel.org>
CC: Rob Herring <robh+dt@...nel.org>,
Serge Semin <Sergey.Semin@...kalelectronics.ru>,
Philipp Zabel <p.zabel@...gutronix.de>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
"David S . Miller" <davem@...emloft.net>,
"Jakub Kicinski" <kuba@...nel.org>,
Kishon Vijay Abraham I <kishon@...com>,
"Vinod Koul" <vkoul@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
"Greg Kroah-Hartman" <gregkh@...uxfoundation.org>,
Stanley Chu <stanley.chu@...iatek.com>,
Min Guo <min.guo@...iatek.com>,
DRI Development <dri-devel@...ts.freedesktop.org>,
DTML <devicetree@...r.kernel.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
<netdev@...r.kernel.org>,
"Linux ARM" <linux-arm-kernel@...ts.infradead.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>, <linux-usb@...r.kernel.org>
Subject: Re: [PATCH v3 07/11] dt-bindings: phy: convert MIP DSI PHY binding
to YAML schema
On Fri, 2020-11-20 at 07:38 +0800, Chun-Kuang Hu wrote:
> Hi, Chunfeng:
>
> Chunfeng Yun <chunfeng.yun@...iatek.com> 於 2020年11月18日 週三 下午4:21寫道：
> >
> > Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml
> >
> > Cc: Chun-Kuang Hu <chunkuang.hu@...nel.org>
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@...iatek.com>
> > ---
> > v3: new patch
> > ---
> > .../display/mediatek/mediatek,dsi.txt | 18 +---
> > .../bindings/phy/mediatek,dsi-phy.yaml | 83 +++++++++++++++++++
> > 2 files changed, 84 insertions(+), 17 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > index f06f24d405a5..8238a86686be 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> > @@ -22,23 +22,7 @@ Required properties:
> > MIPI TX Configuration Module
> > ============================
> >
> > -The MIPI TX configuration module controls the MIPI D-PHY.
> > -
> > -Required properties:
> > -- compatible: "mediatek,<chip>-mipi-tx"
> > -- the supported chips are mt2701, 7623, mt8173 and mt8183.
> > -- reg: Physical base address and length of the controller's registers
> > -- clocks: PLL reference clock
> > -- clock-output-names: name of the output clock line to the DSI encoder
> > -- #clock-cells: must be <0>;
> > -- #phy-cells: must be <0>.
> > -
> > -Optional properties:
> > -- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
> > - the step is 200.
> > -- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
> > - unspecified default values shall be used.
> > -- nvmem-cell-names: Should be "calibration-data"
> > +See phy/mediatek,dsi-phy.yaml
> >
> > Example:
> >
> > diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
> > new file mode 100644
> > index 000000000000..87f8df251ab0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
> > @@ -0,0 +1,83 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2020 MediaTek
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek MIPI Display Serial Interface (DSI) PHY binding
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu@...nel.org>
> > + - Chunfeng Yun <chunfeng.yun@...iatek.com>
>
> Please add Philipp Zabel because he is Mediatek DRM driver maintainer.
Ok
>
> DRM DRIVERS FOR MEDIATEK
> M: Chun-Kuang Hu <chunkuang.hu@...nel.org>
> M: Philipp Zabel <p.zabel@...gutronix.de>
> L: dri-devel@...ts.freedesktop.org
> S: Supported
> F: Documentation/devicetree/bindings/display/mediatek/
>
> > +
> > +description: The MIPI DSI PHY supports up to 4-lane output.
> > +
> > +properties:
> > + $nodename:
> > + pattern: "^dsi-phy@[0-9a-f]+$"
> > +
> > + compatible:
> > + enum:
> > + - mediatek,mt2701-mipi-tx
> > + - mediatek,mt7623-mipi-tx
> > + - mediatek,mt8173-mipi-tx
>
> Add mediatek,mt8183-mipi-tx
Ok, will add it
Thanks
>
> Regards,
> Chun-Kuang.
>
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: PLL reference clock
> > +
> > + clock-output-names:
> > + maxItems: 1
> > +
> > + "#phy-cells":
> > + const: 0
> > +
> > + "#clock-cells":
> > + const: 0
> > +
> > + nvmem-cells:
> > + maxItems: 1
> > + description: A phandle to the calibration data provided by a nvmem device,
> > + if unspecified, default values shall be used.
> > +
> > + nvmem-cell-names:
> > + items:
> > + - const: calibration-data
> > +
> > + drive-strength-microamp:
> > + description: adjust driving current, the step is 200.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + minimum: 2000
> > + maximum: 6000
> > + default: 4600
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-output-names
> > + - "#phy-cells"
> > + - "#clock-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8173-clk.h>
> > + dsi-phy@...15000 {
> > + compatible = "mediatek,mt8173-mipi-tx";
> > + reg = <0x10215000 0x1000>;
> > + clocks = <&clk26m>;
> > + clock-output-names = "mipi_tx0_pll";
> > + drive-strength-microamp = <4000>;
> > + nvmem-cells= <&mipi_tx_calibration>;
> > + nvmem-cell-names = "calibration-data";
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + };
> > +
> > +...
> > --
> > 2.18.0
> >
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