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Date: Sun, 22 Nov 2020 16:16:02 +0100 From: Krzysztof Kozlowski <krzk@...nel.org> To: Sylwester Nawrocki <s.nawrocki@...sung.com> Cc: linux-clk@...r.kernel.org, tomasz.figa@...il.com, cw00.choi@...sung.com, m.szyprowski@...sung.com, sboyd@...nel.org, mturquette@...libre.com, b.zolnierkie@...sung.com, linux-kernel@...r.kernel.org, linux-samsung-soc@...r.kernel.org Subject: Re: [PATCH v5] clk: samsung: Prevent potential endless loop in the PLL ops On Fri, Nov 20, 2020 at 04:57:31PM +0100, Sylwester Nawrocki wrote: > The PLL status polling loops in the set_rate callbacks of some PLLs > have no timeout detection and may become endless loops when something > goes wrong with the PLL. > > For some PLLs there is already the ktime API based timeout detection, > but it will not work in all conditions when .set_rate gets called. > In particular, before the clocksource is initialized or when the > timekeeping is suspended. > > This patch adds a common helper with the PLL status bit polling and > timeout detection. For conditions where the timekeeping API should not > be used a simple readl_relaxed/cpu_relax() busy loop is added with the > iterations limit derived from measurements of readl_relaxed() execution > time for various PLL types and Exynos SoCs variants. > > Actual PLL lock time depends on the P divider value, the VCO frequency > and a constant PLL type specific LOCK_FACTOR and can be calculated as > > lock_time = Pdiv * LOCK_FACTOR / VCO_freq > > For the ktime API use cases a common timeout value of 20 ms is applied > for all the PLLs with an assumption that maximum possible value of Pdiv > is 64, maximum possible LOCK_FACTOR value is 3000 and minimum VCO > frequency is 24 MHz. > > Signed-off-by: Sylwester Nawrocki <s.nawrocki@...sung.com> Reviewed-by: Krzysztof Kozlowski <krzk@...nel.org> Best regards, Krzysztof
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