linux-kernel - Re: [PATCH v2] arm64: dts: sdm845: Add iommus property to qup

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Message-ID: <3ba39a64-122b-ebe9-04b3-3a23478334a4@connolly.tech>
Date:   Mon, 23 Nov 2020 05:16:20 +0000
From:   Caleb Connolly <caleb@...nolly.tech>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>,
        Andy Gross <agross@...nel.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] arm64: dts: sdm845: Add iommus property to qup

On 2020-11-22 03:41, Bjorn Andersson wrote:
> From: Stephen Boyd <swboyd@...omium.org>
>
> The SMMU that sits in front of the QUP needs to be programmed properly
> so that the i2c geni driver can allocate DMA descriptors. Failure to do
> this leads to faults when using devices such as an i2c touchscreen where
> the transaction is larger than 32 bytes and we use a DMA buffer.
>
> arm-smmu 15000000.iommu: Unexpected global fault, this could be serious
> arm-smmu 15000000.iommu:         GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000
>
> Add the right SID and mask so this works.
>
> Signed-off-by: Stephen Boyd <swboyd@...omium.org>
> [bjorn: Define for second QUP as well, be more specific in sdm845.dtsi]
> Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> ---
>   arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 2 ++
>   arch/arm64/boot/dts/qcom/sdm845.dtsi       | 2 ++
>   2 files changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> index 39f23cdcbd02..216a74f0057c 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> @@ -653,10 +653,12 @@ &pm8998_pwrkey {
>   
>   &qupv3_id_0 {
>   	status = "okay";
> +	iommus = <&apps_smmu 0x0 0x3>;
>   };
>   
>   &qupv3_id_1 {
>   	status = "okay";
> +	iommus = <&apps_smmu 0x6c0 0x3>;
>   };
>   
>   &sdhc_2 {
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 6465a6653ad9..d6b7b1bfa202 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1120,6 +1120,7 @@ qupv3_id_0: geniqup@...000 {
>   			clock-names = "m-ahb", "s-ahb";
>   			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
>   				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> +			iommus = <&apps_smmu 0x3 0x0>;
>   			#address-cells = <2>;
>   			#size-cells = <2>;
>   			ranges;
> @@ -1460,6 +1461,7 @@ qupv3_id_1: geniqup@...000 {
>   			clock-names = "m-ahb", "s-ahb";
>   			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
>   				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +			iommus = <&apps_smmu 0x6c3 0x0>;
>   			#address-cells = <2>;
>   			#size-cells = <2>;
>   			ranges;

Tested-By: Caleb Connolly <caleb@...nolly.tech>

Works on the OnePlus 6.