linux-kernel - Re: [PATCH v2] x86/resctrl: Fix AMD L3 QOS CDP enable/disable

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Message-ID: <cd932b15-4094-7f97-a019-057af2aa577c@intel.com>
Date:   Tue, 24 Nov 2020 09:23:23 -0800
From:   Reinette Chatre <reinette.chatre@...el.com>
To:     Babu Moger <babu.moger@....com>, bp@...en8.de
Cc:     fenghua.yu@...el.com, x86@...nel.org, linux-kernel@...r.kernel.org,
        mingo@...hat.com, hpa@...or.com, tglx@...utronix.de
Subject: Re: [PATCH v2] x86/resctrl: Fix AMD L3 QOS CDP enable/disable

Hi Babu,

On 11/20/2020 9:25 AM, Babu Moger wrote:
> When the AMD QoS feature CDP(code and data prioritization) is enabled
> or disabled, the CDP bit in MSR 0000_0C81 is written on one of the
> CPUs in L3 domain(core complex). That is not correct. The CDP bit needs
> to be updated all the logical CPUs in the domain.
> 
> This was not spelled out clearly in the spec earlier. The specification
> has been updated. The updated specification, "AMD64 Technology Platform
> Quality of Service Extensions Publication # 56375 Revision: 1.02 Issue
> Date: October 2020" is available now. Refer the section: Code and Data
> Prioritization.
> 
> Fix the issue by adding a new flag arch_has_per_cpu_cfg in rdt_cache
> data structure.
> 
> The documentation can be obtained at the links below:
> https://developer.amd.com/wp-content/resources/56375.pdf
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
> 
> Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature")
> Signed-off-by: Babu Moger <babu.moger@....com>
> ---
> v2: Taken care of Reinette's comments. Changed the field name to
>      arch_has_per_cpu_cfg to be bit more meaningful about the CPU scope.
>      Also fixed some wordings.
> 
> v1: https://lore.kernel.org/lkml/160469365104.21002.2901190946502347327.stgit@bmoger-ubuntu/
> 
>   arch/x86/kernel/cpu/resctrl/core.c     |    4 ++++
>   arch/x86/kernel/cpu/resctrl/internal.h |    3 +++
>   arch/x86/kernel/cpu/resctrl/rdtgroup.c |    9 +++++++--
>   3 files changed, 14 insertions(+), 2 deletions(-)
> 

...

> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
> index 80fa997fae60..bcd9b517c765 100644
> --- a/arch/x86/kernel/cpu/resctrl/internal.h
> +++ b/arch/x86/kernel/cpu/resctrl/internal.h
> @@ -360,6 +360,8 @@ struct msr_param {
>    *			executing entities
>    * @arch_has_sparse_bitmaps:	True if a bitmap like f00f is valid.
>    * @arch_has_empty_bitmaps:	True if the '0' bitmap is valid.
> + * @arch_has_per_cpu_cfg:	True if QOS_CFG register for this cache
> + * 				level has CPU scope.

Please fixup the spacing to not have spaces before tabs. This will make 
checkpatch happy and fit with in with the rest of the comments for this 
struct.

>    */
>   struct rdt_cache {
>   	unsigned int	cbm_len;
> @@ -369,6 +371,7 @@ struct rdt_cache {
>   	unsigned int	shareable_bits;
>   	bool		arch_has_sparse_bitmaps;
>   	bool		arch_has_empty_bitmaps;
> +	bool		arch_has_per_cpu_cfg;
>   };
>   
>   /**

...

This patch looks good to me.

With the one style comment addressed you can add:
Reviewed-by: Reinette Chatre <reinette.chatre@...el.com>

Thank you very much

Reinette