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Message-ID: <a11f7fb2-6512-484f-70f8-bd9493ab7766@nvidia.com>
Date: Tue, 24 Nov 2020 09:27:06 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: Bjorn Helgaas <helgaas@...nel.org>
CC: <bhelgaas@...gle.com>, <lorenzo.pieralisi@....com>,
<thierry.reding@...il.com>, <jonathanh@...dia.com>,
<linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<kthota@...dia.com>, <mmaddireddy@...dia.com>, <sagar.tv@...il.com>
Subject: Re: [PATCH] PCI/MSI: Set device flag indicating only 32-bit MSI
support
On 11/21/2020 3:00 AM, Bjorn Helgaas wrote:
> External email: Use caution opening links or attachments
>
>
> On Tue, Nov 17, 2020 at 08:27:28PM +0530, Vidya Sagar wrote:
>> There are devices (Ex:- Marvell SATA controller) that don't support
>> 64-bit MSIs and the same is advertised through their MSI capability
>> register.
>
> I *think* you're saying these devices behave correctly per spec: they
> don't support 64-bit MSI, and they don't advertise support for 64-bit
> MSI. Right?
Yes. That is what I intended to say.
>
>> Set no_64bit_msi flag explicitly for such devices in the
>> MSI setup code so that the msi_verify_entries() API would catch
>> if the MSI arch code tries to use 64-bit MSI.
>
> And you want msi_verify_entries() to catch attempts by the arch code
> to assign a 64-bit MSI address?
Yes.
>
> That sounds OK, but the error message ("Device has broken 64-bit MSI")
> is not appropriate if the device is actually *not* broken.
Ok. I didn't change the existing error message. I'll change it to cover
both the scenarios i.e. either the device is broken or the device
doesn't really support 64-bit MSI.
>
>> Signed-off-by: Vidya Sagar <vidyas@...dia.com>
>> ---
>> drivers/pci/msi.c | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
>> index d52d118979a6..af49da28854e 100644
>> --- a/drivers/pci/msi.c
>> +++ b/drivers/pci/msi.c
>> @@ -581,10 +581,12 @@ msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
>> entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
>> entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
>>
>> - if (control & PCI_MSI_FLAGS_64BIT)
>> + if (control & PCI_MSI_FLAGS_64BIT) {
>> entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
>> - else
>> + } else {
>> entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
>> + dev->no_64bit_msi = 1;
>> + }
>>
>> /* Save the initial mask status */
>> if (entry->msi_attrib.maskbit)
>> --
>> 2.17.1
>>
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