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Message-ID: <CAJMQK-gXFBbpmxugme3U0bJ_7TtWdibWWqQHSZLWy0jyeVuUuw@mail.gmail.com>
Date: Tue, 24 Nov 2020 16:25:08 +0800
From: Hsin-Yi Wang <hsinyi@...omium.org>
To: Michael Kao <michael.kao@...iatek.com>
Cc: Zhang Rui <rui.zhang@...el.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Linux PM <linux-pm@...r.kernel.org>,
srv_heupstream@...iatek.com,
Eduardo Valentin <edubezval@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
Devicetree List <devicetree@...r.kernel.org>,
lkml <linux-kernel@...r.kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
Matthias Kaehlcke <mka@...omium.org>
Subject: Re: [v5 2/3] arm64: dts: mt8183: Configure CPU cooling
On Tue, Oct 13, 2020 at 6:24 PM Michael Kao <michael.kao@...iatek.com> wrote:
>
> From: Matthias Kaehlcke <mka@...omium.org>
>
> Add two passive trip points at 68°C and 80°C for the CPU temperature.
>
> Signed-off-by: Matthias Kaehlcke <mka@...omium.org>
> Signed-off-by: Michael Kao <michael.kao@...iatek.com>
Tested-by: Hsin-Yi Wang <hsinyi@...omium.org>
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 56 ++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 1cd093cf33f3..0614f18a1ea2 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/reset-controller/mt8183-resets.h>
> #include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/thermal/thermal.h>
> #include "mt8183-pinfunc.h"
>
> / {
> @@ -450,6 +451,61 @@
> polling-delay = <500>;
> thermal-sensors = <&thermal 0>;
> sustainable-power = <5000>;
> +
> + trips {
> + threshold: trip-point@0 {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + target: trip-point@1 {
> + temperature = <80000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit: cpu-crit {
> + temperature = <115000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&target>;
> + cooling-device = <&cpu0
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu1
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu2
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu3
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>;
> + contribution = <3072>;
> + };
> + map1 {
> + trip = <&target>;
> + cooling-device = <&cpu4
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu5
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu6
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu7
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>;
> + contribution = <1024>;
> + };
> + };
> };
>
> /* The tzts1 ~ tzts6 don't need to polling */
> --
> 2.18.0
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