linux-kernel - [PATCH v2 3/3] MIPS: dts: mscc: add reset support for Luton and Jaguar2

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Date:   Wed, 25 Nov 2020 08:19:20 +0100
From:   Gregory CLEMENT <gregory.clement@...tlin.com>
To:     Sebastian Reichel <sre@...nel.org>, linux-pm@...r.kernel.org,
        linux-kernel@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
        devicetree@...r.kernel.org
Cc:     Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Lars Povlsen <lars.povlsen@...rochip.com>,
        <Steen.Hegelund@...rochip.com>,
        Gregory CLEMENT <gregory.clement@...tlin.com>
Subject: [PATCH v2 3/3] MIPS: dts: mscc: add reset support for Luton and Jaguar2

Allow Luton and Jaguar2 SoCs to use reset feature by adding the reset
node.

Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
---
 arch/mips/boot/dts/mscc/jaguar2.dtsi | 5 +++++
 arch/mips/boot/dts/mscc/luton.dtsi   | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/mips/boot/dts/mscc/jaguar2.dtsi b/arch/mips/boot/dts/mscc/jaguar2.dtsi
index 42b2b0a51ddc..7032fe550277 100644
--- a/arch/mips/boot/dts/mscc/jaguar2.dtsi
+++ b/arch/mips/boot/dts/mscc/jaguar2.dtsi
@@ -60,6 +60,11 @@ cpu_ctrl: syscon@...00000 {
 			reg = <0x70000000 0x2c>;
 		};
 
+		reset@...10008 {
+			compatible = "mscc,jaguar2-chip-reset";
+			reg = <0x71010008 0x4>;
+		};
+
 		intc: interrupt-controller@...00070 {
 			compatible = "mscc,jaguar2-icpu-intr";
 			reg = <0x70000070 0x94>;
diff --git a/arch/mips/boot/dts/mscc/luton.dtsi b/arch/mips/boot/dts/mscc/luton.dtsi
index 2a170b84c5a9..4a26c2874386 100644
--- a/arch/mips/boot/dts/mscc/luton.dtsi
+++ b/arch/mips/boot/dts/mscc/luton.dtsi
@@ -56,6 +56,11 @@ cpu_ctrl: syscon@...00000 {
 			reg = <0x10000000 0x2c>;
 		};
 
+		reset@...70090 {
+			compatible = "mscc,luton-chip-reset";
+			reg = <0x70090 0x4>;
+		};
+
 		intc: interrupt-controller@...00084 {
 			compatible = "mscc,luton-icpu-intr";
 			reg = <0x10000084 0x70>;
-- 
2.29.2