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Message-ID: <d512469f-de04-2f66-ca42-21ec3c5331ba@tik.uni-stuttgart.de>
Date:   Wed, 25 Nov 2020 14:41:19 +0100
From:   "Stefan Bühler" 
        <stefan.buehler@....uni-stuttgart.de>
To:     Thomas Gleixner <tglx@...utronix.de>, sean.v.kelley@...ux.intel.com
Cc:     bhelgaas@...gle.com, bp@...en8.de, corbet@....net,
        kar.hin.ong@...com, linux-doc@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
        mingo@...hat.com, sassmann@...nic.de, x86@...nel.org,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Subject: Re: boot interrupt quirk (also in 4.19.y) breaks serial ports (was:
 [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets)

Hi tglx,

On 11/25/20 12:54 PM, Thomas Gleixner wrote:
> Stefan,
> 
> On Wed, Sep 16 2020 at 12:12, Stefan Bühler wrote:
> 
> sorry for the delay. This fell through the cracks.
> 
>> this quirk breaks our serial ports PCIe card (i.e. we don't see any 
>> output from the connected devices; no idea whether anything we send 
>> reaches them):
>>
>> 05:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa)
>> 06:00.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart)
>> 06:00.1 Bridge: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled)
>> 06:01.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart)
>> 06:01.1 Bridge: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART)
>> function 0 (Disabled)
> 
> Can you please provide the output of:
> 
>  for ID in 05:00.0 06:00.0 06:00.1 06:01.0 06:01.1; do lspci -s $ID -vvv; done
> 

See attachment.

Also I boot the affected systems now with "pci=noioapicquirk", which
"solves" the issue too (instead of patching the kernel).

cheers,
Stefan

View attachment "oxford-serial-lspci.txt" of type "text/plain" (3721 bytes)

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