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Date:   Thu, 26 Nov 2020 19:45:59 +0100
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...ainline.org>
To:     linux-arm-msm@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-pm@...r.kernel.org, ulf.hansson@...aro.org,
        jorge.ramirez-ortiz@...aro.org, broonie@...nel.org,
        lgirdwood@...il.com, daniel.lezcano@...aro.org, nks@...wful.org,
        bjorn.andersson@...aro.org, agross@...nel.org, robh+dt@...nel.org,
        viresh.kumar@...aro.org, rjw@...ysocki.net,
        konrad.dybcio@...ainline.org, martin.botka@...ainline.org,
        marijn.suijten@...ainline.org, phone-devel@...r.kernel.org,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...ainline.org>
Subject: [PATCH 13/13] dt-bindings: cpufreq: qcom-hw: Add bindings for 8998

The OSM programming addition has been done under the
qcom,cpufreq-hw-8998 compatible name: specify the requirement
of two additional register spaces for this functionality.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
---
 .../bindings/cpufreq/qcom,cpufreq-hw.yaml     | 31 ++++++++++++++++---
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/cpufreq/qcom,cpufreq-hw.yaml b/Documentation/devicetree/bindings/cpufreq/qcom,cpufreq-hw.yaml
index 94a56317b14b..f64cea73037e 100644
--- a/Documentation/devicetree/bindings/cpufreq/qcom,cpufreq-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/qcom,cpufreq-hw.yaml
@@ -23,17 +23,21 @@ properties:
           - qcom,cpufreq-epss
 
   reg:
+    description: Base address and size of the RBCPR register region
     minItems: 2
     maxItems: 2
 
   reg-names:
     description:
-      Frequency domain register region for each domain.
-    items:
-      - const: "freq-domain0"
-      - const: "freq-domain1"
+      Frequency domain register region for each domain. If OSM programming
+      does not happen in the bootloader and has to be done in this driver,
+      then also the OSM domain region osm-domain[0-1] has to be provided.
+    minItems: 2
+    maxItems: 2
 
   clock-names:
+    minItems: 2
+    maxItems: 2
     - const: xo
     - const: ref
 
@@ -53,9 +57,28 @@ properties:
       property with phandle to a cpufreq_hw followed by the Domain ID(0/1)
       in the CPU DT node.
 
+allOf:
+ - if:
+     properties:
+       reg-names:
+         contains:
+           const: qcom,cpufreq-hw-8998
+   then:
+     properties:
+       reg:
+         minItems: 4
+         maxItems: 4
+       reg-names:
+         items:
+           - const: "freq-domain0"
+           - const: "freq-domain1"
+           - const: "osm-domain0"
+           - const: "osm-domain1"
+
 required:
   - compatible
   - reg
+  - reg-names
   - clock-names
   - clocks
   - "#freq-domain-cells"
-- 
2.29.2

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