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Date:   Thu, 26 Nov 2020 13:01:14 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     kan.liang@...ux.intel.com, mingo@...nel.org, acme@...nel.org,
        mark.rutland@....com, alexander.shishkin@...ux.intel.com,
        jolsa@...hat.com, eranian@...gle.com
Cc:     christophe.leroy@...roup.eu, npiggin@...il.com,
        linuxppc-dev@...ts.ozlabs.org, mpe@...erman.id.au, will@...nel.org,
        willy@...radead.org, aneesh.kumar@...ux.ibm.com,
        sparclinux@...r.kernel.org, davem@...emloft.net,
        catalin.marinas@....com, linux-arch@...r.kernel.org,
        linux-kernel@...r.kernel.org, ak@...ux.intel.com,
        dave.hansen@...el.com, kirill.shutemov@...ux.intel.com,
        peterz@...radead.org
Subject: [PATCH v2 0/6] perf/mm: Fix PERF_SAMPLE_*_PAGE_SIZE

Hi,

These patches provide generic infrastructure to determine TLB page size from
page table entries alone. Perf will use this (for either data or code address)
to aid in profiling TLB issues.

While most architectures only have page table aligned large pages, some
(notably ARM64, Sparc64 and Power) provide non page table aligned large pages
and need to provide their own implementation of these functions.

I've provided (completely untested) implementations for ARM64, Sparc64 and
Power/8xxx (it looks like I'm still missing Power/Book3s64/hash support).

Changes since -v1:

 - Changed wording to reflect these are page-table sizes; actual TLB sizes
   might vary.
 - added Power/8xx

Barring any objections I'll queue these in tip/perf/core, as these patches fix
the code that's currently in there.


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