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Date:   Thu, 26 Nov 2020 14:10:54 +0100
From:   Michal Simek <monstr@...str.eu>
To:     agriveaux@...tnet.info, michal.simek@...inx.com, robh+dt@...nel.org
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2] ARM: zynq: Add Z-turn board V5



On 26. 11. 20 8:05, agriveaux@...tnet.info wrote:
> From: Alexandre GRIVEAUX <agriveaux@...tnet.info>
> 
> Adding Z-turn board V5 to resolve the change between:
> 
> "Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
> "Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031
> 
> Changes v1 -> v2: Instead of using new board, the v2 using a common devicetree
> for z-turn boards (zynq-zturn-common.dtsi) and for each board a specific DT
> 
> Signed-off-by: Alexandre GRIVEAUX <agriveaux@...tnet.info>
> ---
>  arch/arm/boot/dts/Makefile               |   1 +
>  arch/arm/boot/dts/zynq-zturn-common.dtsi | 112 +++++++++++++++++++++++
>  arch/arm/boot/dts/zynq-zturn-v5.dts      |  15 +++
>  arch/arm/boot/dts/zynq-zturn.dts         | 101 +-------------------
>  4 files changed, 129 insertions(+), 100 deletions(-)
>  create mode 100644 arch/arm/boot/dts/zynq-zturn-common.dtsi
>  create mode 100644 arch/arm/boot/dts/zynq-zturn-v5.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index ce66ffd5a1bb..3de85fe42f76 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1302,6 +1302,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
>  	zynq-zc770-xm013.dtb \
>  	zynq-zed.dtb \
>  	zynq-zturn.dtb \
> +	zynq-zturn-v5.dtb \
>  	zynq-zybo.dtb \
>  	zynq-zybo-z7.dtb
>  dtb-$(CONFIG_MACH_ARMADA_370) += \
> diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/zynq-zturn-common.dtsi
> new file mode 100644
> index 000000000000..84f3c85c5bab
> --- /dev/null
> +++ b/arch/arm/boot/dts/zynq-zturn-common.dtsi
> @@ -0,0 +1,112 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + *  Copyright (C) 2015 Andrea Merello <adnrea.merello@...il.com>
> + *  Copyright (C) 2017 Alexander Graf <agraf@...e.de>
> + *
> + *  Based on zynq-zed.dts which is:
> + *  Copyright (C) 2011 - 2014 Xilinx
> + *  Copyright (C) 2012 National Instruments Corp.
> + *
> + */
> +
> +/dts-v1/;
> +/include/ "zynq-7000.dtsi"
> +
> +/ {
> +	compatible = "xlnx,zynq-7000";
> +
> +	aliases {
> +		ethernet0 = &gem0;
> +		serial0 = &uart1;
> +		serial1 = &uart0;
> +		mmc0 = &sdhci0;
> +	};
> +
> +	memory@0 {
> +		device_type = "memory";
> +		reg = <0x0 0x40000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +		usr-led1 {
> +			label = "usr-led1";
> +			gpios = <&gpio0 0x0 0x1>;
> +			default-state = "off";
> +		};
> +
> +		usr-led2 {
> +			label = "usr-led2";
> +			gpios = <&gpio0 0x9 0x1>;
> +			default-state = "off";
> +		};
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		autorepeat;
> +		K1 {
> +			label = "K1";
> +			gpios = <&gpio0 0x32 0x1>;
> +			linux,code = <0x66>;
> +			wakeup-source;
> +			autorepeat;
> +		};
> +	};
> +};
> +
> +&clkc {
> +	ps-clk-frequency = <33333333>;
> +};
> +
> +&gem0 {
> +	status = "okay";
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ethernet_phy>;
> +
> +	ethernet_phy: ethernet-phy@0 {
> +	};
> +};
> +
> +&sdhci0 {
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	status = "okay";
> +};
> +
> +&usb0 {
> +	status = "okay";
> +	dr_mode = "host";
> +};
> +
> +&can0 {
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +	clock-frequency = <400000>;
> +
> +	stlm75@49 {
> +		status = "okay";
> +		compatible = "lm75";
> +		reg = <0x49>;
> +	};
> +
> +	accelerometer@53 {
> +		compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
> +		reg = <0x53>;
> +		interrupt-parent = <&intc>;
> +		interrupts = <0x0 0x1e 0x4>;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/zynq-zturn-v5.dts b/arch/arm/boot/dts/zynq-zturn-v5.dts
> new file mode 100644
> index 000000000000..536632a09a25
> --- /dev/null
> +++ b/arch/arm/boot/dts/zynq-zturn-v5.dts
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +/include/ "zynq-zturn-common.dtsi"
> +
> +/ {
> +	model = "Zynq Z-Turn MYIR Board V5";
> +	compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000";
> +};
> +
> +&gem0 {
> +	ethernet_phy: ethernet-phy@0 {
> +		reg = <0x3>;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts
> index 5ec616ebca08..620b24a25e06 100644
> --- a/arch/arm/boot/dts/zynq-zturn.dts
> +++ b/arch/arm/boot/dts/zynq-zturn.dts
> @@ -1,114 +1,15 @@
>  // SPDX-License-Identifier: GPL-2.0
> -/*
> - *  Copyright (C) 2015 Andrea Merello <adnrea.merello@...il.com>
> - *  Copyright (C) 2017 Alexander Graf <agraf@...e.de>
> - *
> - *  Based on zynq-zed.dts which is:
> - *  Copyright (C) 2011 - 2014 Xilinx
> - *  Copyright (C) 2012 National Instruments Corp.
> - *
> - */
>  
>  /dts-v1/;
> -/include/ "zynq-7000.dtsi"
> +/include/ "zynq-zturn-common.dtsi"
>  
>  / {
>  	model = "Zynq Z-Turn MYIR Board";
>  	compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
> -
> -	aliases {
> -		ethernet0 = &gem0;
> -		serial0 = &uart1;
> -		serial1 = &uart0;
> -		mmc0 = &sdhci0;
> -	};
> -
> -	memory@0 {
> -		device_type = "memory";
> -		reg = <0x0 0x40000000>;
> -	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
> -	gpio-leds {
> -		compatible = "gpio-leds";
> -		usr-led1 {
> -			label = "usr-led1";
> -			gpios = <&gpio0 0x0 0x1>;
> -			default-state = "off";
> -		};
> -
> -		usr-led2 {
> -			label = "usr-led2";
> -			gpios = <&gpio0 0x9 0x1>;
> -			default-state = "off";
> -		};
> -	};
> -
> -	gpio-keys {
> -		compatible = "gpio-keys";
> -		autorepeat;
> -		K1 {
> -			label = "K1";
> -			gpios = <&gpio0 0x32 0x1>;
> -			linux,code = <0x66>;
> -			wakeup-source;
> -			autorepeat;
> -		};
> -	};
> -};
> -
> -&clkc {
> -	ps-clk-frequency = <33333333>;
>  };
>  
>  &gem0 {
> -	status = "okay";
> -	phy-mode = "rgmii-id";
> -	phy-handle = <&ethernet_phy>;
> -
>  	ethernet_phy: ethernet-phy@0 {
>  		reg = <0x0>;
>  	};
>  };
> -
> -&sdhci0 {
> -	status = "okay";
> -};
> -
> -&uart0 {
> -	status = "okay";
> -};
> -
> -&uart1 {
> -	status = "okay";
> -};
> -
> -&usb0 {
> -	status = "okay";
> -	dr_mode = "host";
> -};
> -
> -&can0 {
> -	status = "okay";
> -};
> -
> -&i2c0 {
> -	status = "okay";
> -	clock-frequency = <400000>;
> -
> -	stlm75@49 {
> -		status = "okay";
> -		compatible = "lm75";
> -		reg = <0x49>;
> -	};
> -
> -	accelerometer@53 {
> -		compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
> -		reg = <0x53>;
> -		interrupt-parent = <&intc>;
> -		interrupts = <0x0 0x1e 0x4>;
> -	};
> -};
> 

Applied.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

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