linux-kernel - Re: [PATCH v4 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek

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Message-ID: <54eee2dd-21d5-e796-d5a1-eaf7097a9745@arm.com>
Date:   Thu, 26 Nov 2020 16:15:58 +0000
From:   Robin Murphy <robin.murphy@....com>
To:     Yong Wu <yong.wu@...iatek.com>, Joerg Roedel <joro@...tes.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Rob Herring <robh+dt@...nel.org>, Will Deacon <will@...nel.org>
Cc:     youlin.pei@...iatek.com, devicetree@...r.kernel.org,
        Nicolas Boichat <drinkcat@...omium.org>,
        srv_heupstream@...iatek.com, chao.hao@...iatek.com,
        kernel-team@...roid.com, linux-kernel@...r.kernel.org,
        Evan Green <evgreen@...omium.org>,
        Tomasz Figa <tfiga@...gle.com>,
        iommu@...ts.linux-foundation.org,
        linux-mediatek@...ts.infradead.org,
        Krzysztof Kozlowski <krzk@...nel.org>, anan.sun@...iatek.com,
        Greg Kroah-Hartman <gregkh@...gle.com>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v4 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for
 MediaTek

On 2020-11-11 12:38, Yong Wu wrote:
> The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> 34bit.

Yay, I love how simple the actual change becomes now!

Reviewed-by: Robin Murphy <robin.murphy@....com>

> Signed-off-by: Yong Wu <yong.wu@...iatek.com>
> ---
>   drivers/iommu/io-pgtable-arm-v7s.c | 7 ++++---
>   drivers/iommu/mtk_iommu.c          | 2 +-
>   2 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index 0b3c5b904ddc..5601dc8bf810 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -45,9 +45,10 @@
>   /*
>    * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2,
>    * and 12 bits in a page.
> + * MediaTek extend 2 bits to reach 34bits, 14 bits at lvl1 and 8 bits at lvl2.
>    */
>   #define ARM_V7S_ADDR_BITS		32
> -#define _ARM_V7S_LVL_BITS(lvl, cfg)	((lvl) == 1 ? 12 : 8)
> +#define _ARM_V7S_LVL_BITS(lvl, cfg)	((lvl) == 1 ? ((cfg)->ias - 20) : 8)
>   #define ARM_V7S_LVL_SHIFT(lvl)		((lvl) == 1 ? 20 : 12)
>   #define ARM_V7S_TABLE_SHIFT		10
>   
> @@ -61,7 +62,7 @@
>   #define _ARM_V7S_IDX_MASK(lvl, cfg)	(ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
>   #define ARM_V7S_LVL_IDX(addr, lvl, cfg)	({				\
>   	int _l = lvl;							\
> -	((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> +	((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
>   })
>   
>   /*
> @@ -754,7 +755,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
>   {
>   	struct arm_v7s_io_pgtable *data;
>   
> -	if (cfg->ias > ARM_V7S_ADDR_BITS)
> +	if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
>   		return NULL;
>   
>   	if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index ec3c87d4b172..55f9b329e637 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -319,7 +319,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
>   			IO_PGTABLE_QUIRK_TLBI_ON_MAP |
>   			IO_PGTABLE_QUIRK_ARM_MTK_EXT,
>   		.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
> -		.ias = 32,
> +		.ias = 34,
>   		.oas = 35,
>   		.tlb = &mtk_iommu_flush_ops,
>   		.iommu_dev = data->dev,
>