linux-kernel - Re: boot interrupt quirk (also in 4.19.y) breaks serial ports (was: [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets)

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <7b54abab-fe38-4035-7c23-1f7456359c9e@tik.uni-stuttgart.de>
Date:   Fri, 27 Nov 2020 10:17:02 +0100
From:   "Stefan Bühler" 
        <stefan.buehler@....uni-stuttgart.de>
To:     Thomas Gleixner <tglx@...utronix.de>, sean.v.kelley@...ux.intel.com
Cc:     bhelgaas@...gle.com, bp@...en8.de, corbet@....net,
        kar.hin.ong@...com, linux-doc@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
        mingo@...hat.com, sassmann@...nic.de, x86@...nel.org,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Subject: Re: boot interrupt quirk (also in 4.19.y) breaks serial ports (was:
 [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets)

Hi tglx,

On 11/27/20 12:45 AM, Thomas Gleixner wrote:
> Stefan,
> 
> On Wed, Nov 25 2020 at 14:41, Stefan Bühler wrote:
>> On 11/25/20 12:54 PM, Thomas Gleixner wrote:
>>> On Wed, Sep 16 2020 at 12:12, Stefan Bühler wrote:
>>> Can you please provide the output of:
>>>
>>>  for ID in 05:00.0 06:00.0 06:00.1 06:01.0 06:01.1; do lspci -s $ID -vvv; done
>>
>> 05:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode])
>>      ...
>> 	Capabilities: <access denied>
> 
> Can you please run this as root so the Capabilities are accessible?

My bad, sorry. I did intend to run it as root, but should have checked
the output.  Again see attached file.


While we're at it: the EEPROM for the PEX8112 is:

00000000  5a 03 3c 00 10 00 00 00  00 00 00 00 b5 10 12 81  |Z.<.............|
00000010  64 00 20 00 00 00 00 01  04 00 01 00 0c 10 00 fe  |d. .............|
00000020  fe 03 20 10 f0 10 00 00  00 10 33 00 00 00 70 00  |.. .......3...p.|
00000030  00 00 11 00 48 00 00 00  00 00 34 00 50 00 00 00  |....H.....4.P...|
00000040  04 00 55 66 77 88                                 |..Ufw.|
00000046

(This is what the firmware tool provided to me writes, although I think 
the cards usually came pre-flashed with it.  They gave me the tool 
because on some cards the second function on OX16PCI954 was sometimes 
uninitialized, came up with device id 0x9511 "8-bit bus" 
(PCI_DEVICE_ID_OXSEMI_16PCI95N) and the kernel tries to treat it as UART 
too.)

I think some time ago I found a PDF to decode this here:
https://www.broadcom.com/products/pcie-switches-bridges/pcie-bridges/pex8112#documentation

But the broadcom site is completely broken right now (at least for me; 
there own search for "PEX 8112" links it, but then it says "not found").

Anyway, back then I decoded this to:

- `0x5A 0x03`: Magic Header, contains register and shared memory settings
- `0x003C` = 60 bytes for configs (10 registers):
  - `@...010`: `0x00000000` -- BAR0: Locate anywhere in 32-bit
  - `@...000`: `0x811210B5` -- Vendor `10B5`, Device `8112` (default)
  - `@...064`: `0x00000020` -- Device Capability: Enable "Support 8-bit Tag" field
  - `@...100`: `0x00010004` -- Power Budget Enhanced Capability Header (default)
  - `@...00C`: `0x03FEFE00` -- PCI Control:
    - PCI-To-PCI Express Retry Count set to 0xFE (default: `0x80`)
    - PCI Express-to-PCI Retry Count set to 0xFE (default: `0x00`)
  - `@...020`: `0x000010F0` -- GPIO Control
    - GPIO[1-3] Output enable (GPIO[0] is Output enabled by default)
    - GPIO Diagnostic Select: `10b` (default: `01b`)
  - `@...000`: `0x00000033` -- Device Initialization (default)
  - `@...070`: `0x00110000` -- Link control: default
  - `@...048`: `0x00000000` -- Device-Specific Control (default 0)
  - `@...034`: `0x00000050` -- PCI Capability pointer `0x50` (default: `0x40`)
    - Skips (disables) Power Management Capability
    - Remaining: MSI and PCI Express
- `0x0004` bytes for shared memory:
  - `0x55`, `0x66`, `0x77`, `0x88`


TLDR: the most notable part probably being "disabling Power Management 
Capability" by the EEPROM.

cheers,
Stefan

View attachment "oxford-serial-lspci.txt" of type "text/plain" (5194 bytes)