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Message-Id: <20201127104930.1981497-3-enric.balletbo@collabora.com>
Date: Fri, 27 Nov 2020 11:49:29 +0100
From: Enric Balletbo i Serra <enric.balletbo@...labora.com>
To: linux-kernel@...r.kernel.org
Cc: Collabora Kernel ML <kernel@...labora.com>,
Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: [PATCH 2/3] arm64: dts: mt8183: Add iommu and larb nodes
Add iommu and larb nodes to the MT8183.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 ++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index da7212e21fdf..ba9ff192cda3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8183-larb-port.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
#include <dt-bindings/phy/phy.h>
@@ -521,6 +522,15 @@ systimer: timer@...17000 {
clock-names = "clk13m";
};
+ iommu: iommu@...05000 {
+ compatible = "mediatek,mt8183-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
+ &larb4 &larb5 &larb6>;
+ #iommu-cells = <1>;
+ };
+
gce: mailbox@...38000 {
compatible = "mediatek,mt8183-gce";
reg = <0 0x10238000 0 0x4000>;
@@ -968,6 +978,16 @@ dsi0: dsi@...14000 {
phy-names = "dphy";
};
+ larb0: larb@...17000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x14017000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clock-names = "apb", "smi";
+ };
+
smi_common: smi@...19000 {
compatible = "mediatek,mt8183-smi-common", "syscon";
reg = <0 0x14019000 0 0x1000>;
@@ -984,18 +1004,57 @@ imgsys: syscon@...20000 {
#clock-cells = <1>;
};
+ larb5: larb@...21000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x15021000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>,
+ <&mmsys CLK_MM_GALS_IMG2MM>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
+ };
+
+ larb2: larb@...2f000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x1502f000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>,
+ <&mmsys CLK_MM_GALS_IPU2MM>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
+ };
+
vdecsys: syscon@...00000 {
compatible = "mediatek,mt8183-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb1: larb@...10000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
+ };
+
vencsys: syscon@...00000 {
compatible = "mediatek,mt8183-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb4: larb@...10000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x17010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vencsys CLK_VENC_LARB>,
+ <&vencsys CLK_VENC_LARB>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
+ };
+
ipu_conn: syscon@...00000 {
compatible = "mediatek,mt8183-ipu_conn", "syscon";
reg = <0 0x19000000 0 0x1000>;
@@ -1025,5 +1084,25 @@ camsys: syscon@...00000 {
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb6: larb@...01000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x1a001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>,
+ <&mmsys CLK_MM_GALS_CAM2MM>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
+ };
+
+ larb3: larb@...02000 {
+ compatible = "mediatek,mt8183-smi-larb";
+ reg = <0 0x1a002000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>,
+ <&mmsys CLK_MM_GALS_IPU12MM>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
+ };
};
};
--
2.29.2
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