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Message-Id: <20201127104930.1981497-2-enric.balletbo@collabora.com>
Date: Fri, 27 Nov 2020 11:49:28 +0100
From: Enric Balletbo i Serra <enric.balletbo@...labora.com>
To: linux-kernel@...r.kernel.org
Cc: Collabora Kernel ML <kernel@...labora.com>,
Jitao Shi <jitao.shi@...iatek.com>,
Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: [PATCH 1/3] arm64: dts: mt8183: Add dsi node
From: Jitao Shi <jitao.shi@...iatek.com>
Add dsi and mipitx nodes to the MT8183.
Signed-off-by: Jitao Shi <jitao.shi@...iatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 31 ++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 7839480df075..da7212e21fdf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -892,10 +892,27 @@ mmc1: mmc@...40000 {
status = "disabled";
};
+ mipi_tx0: mipi-dphy@...50000 {
+ compatible = "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11e50000 0 0x1000>;
+ clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
+ clock-names = "ref_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clock-output-names = "mipi_tx0_pll";
+ nvmem-cells = <&mipi_tx_calibration>;
+ nvmem-cell-names = "calibration-data";
+ };
+
efuse: efuse@...10000 {
compatible = "mediatek,mt8183-efuse",
"mediatek,efuse";
reg = <0 0x11f10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ mipi_tx_calibration: calib@190 {
+ reg = <0x190 0xc>;
+ };
};
u3phy: usb-phy@...40000 {
@@ -937,6 +954,20 @@ mmsys: syscon@...00000 {
#clock-cells = <1>;
};
+ dsi0: dsi@...14000 {
+ compatible = "mediatek,mt8183-dsi";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ mediatek,syscon-dsi = <&mmsys 0x140>;
+ clocks = <&mmsys CLK_MM_DSI0_MM>,
+ <&mmsys CLK_MM_DSI0_IF>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ };
+
smi_common: smi@...19000 {
compatible = "mediatek,mt8183-smi-common", "syscon";
reg = <0 0x14019000 0 0x1000>;
--
2.29.2
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