linux-kernel - Re: [PATCH v6 00/11] clk: at91: clk-master: re-factor master clock

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Message-ID: <51c33456-5627-3d6f-2996-b7f617b4dc5a@microchip.com>
Date:   Fri, 27 Nov 2020 12:12:22 +0000
From:   <Claudiu.Beznea@...rochip.com>
To:     <mturquette@...libre.com>, <sboyd@...nel.org>,
        <Nicolas.Ferre@...rochip.com>, <alexandre.belloni@...tlin.com>,
        <Ludovic.Desroches@...rochip.com>, <robh+dt@...nel.org>
CC:     <linux-clk@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH v6 00/11] clk: at91: clk-master: re-factor master clock

I have just noticed that the title of this cover letter is wrong.
It should have been:

"clk: at91: adapt for dvfs"

Please let me know if you want me to send a new version for this update.

Thank you,
Claudiu

On 19.11.2020 17:43, Claudiu Beznea wrote:
> Hi,
> 
> SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be
> obtained from CPU PLL. The hardware block diagram for clock feeding the
> CPU is as follows:
> 
>                                +--------+
>                            +-->|divider1|--> CPU clock
>                            |   +--------+
> +--------+   +----------+  |   +--------+
> |CPU PLL |-->|prescaller|--+-->|divider0|--> MCK0 clock
> +--------+   +----------+      +--------+
> 
> When switching CPU clock frequencies the MCK0 is also changed by DVFS
> driver to avoid its over/under clocking (depending on CPU clock frequency
> requested by DVFS algorithms). Some of IPs feed by MCK0 are MCK0 glich
> aware, some are not. For this MCK0 was removed from the parents list of
> the IPs which are not MCK0 glitch aware (patch 7/11).
> 
> This series adapt AT91 clocks (mostly sam9x60-pll and master clock drivers)
> so that runtime changes of these clocks to be allowed.
> 
> The CPU clock was registered from prescaller clock (see above diagram)
> and no software control has been added for divider1 because the frequencies
> supported by SAMA7G5's CPU could be directly obtained from CPU PLL +
> prescaller.
> 
> On top of this series I also added a fix for sama7g5.c code (patch 1/11).
> Please let me know if you would like me to send this one separtely (it
> would be nice if this fix could be integrated in 5.10).
> 
> Changes were tested on SAMA5D2, SAMA5D3, SAM9X60 and SAMA7G5.
> 
> Thank you,
> Claudiu Beznea
> 
> Changes in v6:
> - remove if (clk_hw_get_flags(hw) & CLK_SET_RATE_GATE) in patch 10/11 as
>   we use different clock ops now for pres, div supporting run-time changes
>   
> Changes in v5:
> - use separate clk_ops for PLLs and master clock div, pres supporting
>   run-time changes (patches 6/11, 10/11)
> - use unsigned long type for f member of struct typeof(sama7g5_plls)
> - document the usage of CLK_IS_CRITICAL
> 
> Changes in v4:
> - added Reviewed-by, Tested-by tags forgoten in v3
> 
> Changes in v3:
> - collected Reviewed-by, Tested-by tags
> - add patches 4/11, 5/11, 9/11
> - in patch 10/11 use CLK_SET_RATE_GATE on MCK div and MCK pres for all
>   the platforms except sama7g5
> 
> Changes in v2:
> - s/at91rm9200_mck_lock/at91sam9260_mck_lock in patch 7/8
> 
> Claudiu Beznea (7):
>   clk: at91: sama7g5: fix compilation error
>   clk: at91: clk-sam9x60-pll: allow runtime changes for pll
>   clk: at91: sama7g5: remove mck0 from parent list of other clocks
>   clk: at91: sama7g5: decrease lower limit for MCK0 rate
>   clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
>   clk: at91: clk-master: re-factor master clock
>   clk: at91: sama7g5: register cpu clock
> 
> Eugen Hristev (4):
>   dt-bindings: clock: at91: add sama7g5 pll defines
>   clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and
>     referenced in DT
>   clk: at91: clk-master: add 5th divisor for mck master
>   clk: at91: sama7g5: add 5th divisor for mck0 layout and
>     characteristics
> 
>  drivers/clk/at91/at91rm9200.c      |  21 ++-
>  drivers/clk/at91/at91sam9260.c     |  26 ++-
>  drivers/clk/at91/at91sam9g45.c     |  32 +++-
>  drivers/clk/at91/at91sam9n12.c     |  36 ++--
>  drivers/clk/at91/at91sam9rl.c      |  23 ++-
>  drivers/clk/at91/at91sam9x5.c      |  28 ++-
>  drivers/clk/at91/clk-master.c      | 337 ++++++++++++++++++++++++++++++++-----
>  drivers/clk/at91/clk-sam9x60-pll.c | 145 ++++++++++++++--
>  drivers/clk/at91/dt-compat.c       |  15 +-
>  drivers/clk/at91/pmc.h             |  22 ++-
>  drivers/clk/at91/sam9x60.c         |  45 +++--
>  drivers/clk/at91/sama5d2.c         |  42 +++--
>  drivers/clk/at91/sama5d3.c         |  38 +++--
>  drivers/clk/at91/sama5d4.c         |  40 +++--
>  drivers/clk/at91/sama7g5.c         | 223 ++++++++++++++++--------
>  include/dt-bindings/clock/at91.h   |  11 ++
>  16 files changed, 840 insertions(+), 244 deletions(-)
>