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Message-ID: <20201127151022.GQ2073444@lunn.ch>
Date: Fri, 27 Nov 2020 16:10:22 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Lukasz Majewski <lukma@...x.de>
Cc: Vladimir Oltean <olteanv@...il.com>,
Fugang Duan <fugang.duan@....com>,
"David S . Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>, netdev@...r.kernel.org,
Fabio Estevam <festevam@...il.com>,
Vivien Didelot <vivien.didelot@...il.com>,
NXP Linux Team <linux-imx@....com>,
Florian Fainelli <f.fainelli@...il.com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Peng Fan <peng.fan@....com>, stefan.agner@...adex.com,
krzk@...nel.org, Shawn Guo <shawnguo@...nel.org>
Subject: Re: [RFC 0/4] net: l2switch: Provide support for L2 switch on i.MX28
SoC
On Fri, Nov 27, 2020 at 10:25:28AM +0100, Lukasz Majewski wrote:
> Hi Andrew,
>
> > > > I would push back and say that the switch offers bridge
> > > > acceleration for the FEC.
> > >
> > > Am I correct, that the "bridge acceleration" means in-hardware
> > > support for L2 packet bridging?
> >
> > You should think of the hardware as an accelerator, not a switch. The
> > hardware is there to accelerate what linux can already do. You setup a
> > software bridge in linux, and then offload L2 switching to the
> > accelerator. You setup vlans in linux, and then offload the filtering
> > of them to the accelerator. If there is something linux can do, but
> > the hardware cannot accelerate, you leave linux to do it in software.
>
> Ok.
>
> >
> > > Do you propose to catch some kind of notification when user calls:
> > >
> > > ip link add name br0 type bridge; ip link set br0 up;
> > > ip link set lan1 up; ip link set lan2 up;
> > > ip link set lan1 master br0; ip link set lan2 master br0;
> > > bridge link
> > >
> > > And then configure the FEC driver to use this L2 switch driver?
> >
> > That is what switchdev does. There are various hooks in the network
> > stack which call into switchdev to ask it to offload operations to the
> > accelerator.
>
> Ok.
>
> >
> > > The differences from "normal" DSA switches:
> > >
> > > 1. It uses mapped memory (for its register space) for
> > > configuration/statistics gathering (instead of e.g. SPI, I2C)
> Hmm...
>
> I cannot find such chapter in the official documentation from NXP:
> "VFxxx Controller Reference Manual, Rev. 0, 10/2016"
I have
Vybrid Reference Manual
F-Series
Document Number: VYBRIDRM
Rev 7, 06/2014
Andrew
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