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Message-Id: <20201128142839.517949-11-paul.kocialkowski@bootlin.com>
Date: Sat, 28 Nov 2020 15:28:30 +0100
From: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
To: linux-media@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-doc@...r.kernel.org, devel@...verdev.osuosl.org,
linux-sunxi@...glegroups.com
Cc: Yong Deng <yong.deng@...ewell.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Maxime Ripard <mripard@...nel.org>,
Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...l.net>,
Paul Kocialkowski <paul.kocialkowski@...tlin.com>,
Jonathan Corbet <corbet@....net>,
Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>,
Helen Koike <helen.koike@...labora.com>,
Dafna Hirschfeld <dafna.hirschfeld@...labora.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
Hans Verkuil <hans.verkuil@...co.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
kevin.lhopital@...mail.com
Subject: [PATCH v2 10/19] ARM: dts: sun8i: v3s: Add CSI1 controller port for parallel input
Since the CSI controller binding is getting a bit more complex due
to the addition of MIPI CSI-2 bridge support, make the ports node
explicit with the parallel port.
This way, it's clear that the controller only supports parallel
interface input and there's no confusion about the port number.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 7b2d684aeb97..7926c8b2ac5e 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -540,6 +540,15 @@ csi1: camera@...4000 {
clock-names = "bus", "mod", "ram";
resets = <&ccu RST_BUS_CSI>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_in_parallel: port@0 {
+ reg = <0>;
+ };
+ };
};
gic: interrupt-controller@...1000 {
--
2.29.2
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