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Message-Id: <20201128142839.517949-9-paul.kocialkowski@bootlin.com>
Date: Sat, 28 Nov 2020 15:28:28 +0100
From: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
To: linux-media@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-doc@...r.kernel.org, devel@...verdev.osuosl.org,
linux-sunxi@...glegroups.com
Cc: Yong Deng <yong.deng@...ewell.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Maxime Ripard <mripard@...nel.org>,
Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...l.net>,
Paul Kocialkowski <paul.kocialkowski@...tlin.com>,
Jonathan Corbet <corbet@....net>,
Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>,
Helen Koike <helen.koike@...labora.com>,
Dafna Hirschfeld <dafna.hirschfeld@...labora.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
Hans Verkuil <hans.verkuil@...co.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
kevin.lhopital@...mail.com
Subject: [PATCH v2 08/19] ARM: dts: sun8i: a83t: Add CSI controller ports
Since the CSI controller binding is getting a bit more complex due
to the addition of MIPI CSI-2 bridge support, make the ports node
explicit with the parallel and MIPI CSI-2 bridge ports.
This way, it's clear that the controller supports both parallel and
MIPI CSI-2 interface inputs and there's no confusion about their port
number.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c010b27fdb6a..3ce030f7e05d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1062,7 +1062,17 @@ csi: camera@...0000 {
resets = <&ccu RST_BUS_CSI>;
status = "disabled";
- csi_in: port {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_in_parallel: port@0 {
+ reg = <0>;
+ };
+
+ csi_in_mipi_csi2_bridge: port@1 {
+ reg = <1>;
+ };
};
};
--
2.29.2
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