linux-kernel - Re: [NEEDS-REVIEW] [PATCH v15 03/26] x86/fpu/xstate: Introduce CET MSR XSAVES supervisor states

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Date:   Mon, 30 Nov 2020 10:06:44 -0800
From:   "Yu, Yu-cheng" <yu-cheng.yu@...el.com>
To:     Dave Hansen <dave.hansen@...el.com>, x86@...nel.org,
        "H. Peter Anvin" <hpa@...or.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
        linux-doc@...r.kernel.org, linux-mm@...ck.org,
        linux-arch@...r.kernel.org, linux-api@...r.kernel.org,
        Arnd Bergmann <arnd@...db.de>,
        Andy Lutomirski <luto@...nel.org>,
        Balbir Singh <bsingharora@...il.com>,
        Borislav Petkov <bp@...en8.de>,
        Cyrill Gorcunov <gorcunov@...il.com>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Eugene Syromiatnikov <esyr@...hat.com>,
        Florian Weimer <fweimer@...hat.com>,
        "H.J. Lu" <hjl.tools@...il.com>, Jann Horn <jannh@...gle.com>,
        Jonathan Corbet <corbet@....net>,
        Kees Cook <keescook@...omium.org>,
        Mike Kravetz <mike.kravetz@...cle.com>,
        Nadav Amit <nadav.amit@...il.com>,
        Oleg Nesterov <oleg@...hat.com>, Pavel Machek <pavel@....cz>,
        Peter Zijlstra <peterz@...radead.org>,
        Randy Dunlap <rdunlap@...radead.org>,
        "Ravi V. Shankar" <ravi.v.shankar@...el.com>,
        Vedvyas Shanbhogue <vedvyas.shanbhogue@...el.com>,
        Dave Martin <Dave.Martin@....com>,
        Weijiang Yang <weijiang.yang@...el.com>,
        Pengfei Xu <pengfei.xu@...el.com>
Subject: Re: [NEEDS-REVIEW] [PATCH v15 03/26] x86/fpu/xstate: Introduce CET
 MSR XSAVES supervisor states

On 11/30/2020 9:45 AM, Dave Hansen wrote:
> On 11/10/20 8:21 AM, Yu-cheng Yu wrote:
>> Control-flow Enforcement Technology (CET) adds five MSRs.  Introduce
>> them and their XSAVES supervisor states:
>>
>>      MSR_IA32_U_CET (user-mode CET settings),
>>      MSR_IA32_PL3_SSP (user-mode Shadow Stack pointer),
>>      MSR_IA32_PL0_SSP (kernel-mode Shadow Stack pointer),
>>      MSR_IA32_PL1_SSP (Privilege Level 1 Shadow Stack pointer),
>>      MSR_IA32_PL2_SSP (Privilege Level 2 Shadow Stack pointer).
> 
> This patch goes into a bunch of XSAVE work that this changelog only
> briefly touches on.  I think it needs to be beefed up a bit.

I will do that.

> 
>> @@ -835,8 +843,19 @@ void __init fpu__init_system_xstate(void)
>>   	 * Clear XSAVE features that are disabled in the normal CPUID.
>>   	 */
>>   	for (i = 0; i < ARRAY_SIZE(xsave_cpuid_features); i++) {
>> -		if (!boot_cpu_has(xsave_cpuid_features[i]))
>> -			xfeatures_mask_all &= ~BIT_ULL(i);
>> +		if (xsave_cpuid_features[i] == X86_FEATURE_SHSTK) {
>> +			/*
>> +			 * X86_FEATURE_SHSTK and X86_FEATURE_IBT share
>> +			 * same states, but can be enabled separately.
>> +			 */
>> +			if (!boot_cpu_has(X86_FEATURE_SHSTK) &&
>> +			    !boot_cpu_has(X86_FEATURE_IBT))
>> +				xfeatures_mask_all &= ~BIT_ULL(i);
>> +		} else {
>> +			if ((xsave_cpuid_features[i] == -1) ||
> 
> Where did the -1 come from?  Was that introduced earlier in this series?
>   I don't see any way a xsave_cpuid_features[] can be -1 in the current tree.
> 

Yes, we used to have a hole in xsave_cpuid_features[] and put -1 there. 
Do we want to keep this in case we again have holes in the future?

>> +			    !boot_cpu_has(xsave_cpuid_features[i]))
>> +				xfeatures_mask_all &= ~BIT_ULL(i);
>> +		}
>>   	}
> 
> Do we have any other spots in the kernel where we care about:
> 
> 	boot_cpu_has(X86_FEATURE_SHSTK) ||
> 	boot_cpu_has(X86_FEATURE_IBT)
> 
> ?  If so, we could also address this by declaring a software-defined
> X86_FEATURE_CET and then setting it if SHSTK||IBT is supported, then we
> just put that one feature in xsave_cpuid_features[].

That is a better solution.  I will look into that.

> 
> I'm also not crazy about the loop as it is.  I'd much rather see this in
> a helper like:
> 
> bool cpu_supports_xsave_deps(int xfeature)
> {
> 	bool ret;
> 
> 	ret = boot_cpu_has(xsave_cpuid_features[xfeature])
> 
> 	/*
> 	 * X86_FEATURE_SHSTK is checked in xsave_cpuid_features()
> 	 * but the CET states are needed if either SHSTK or IBT are
> 	 * available.
> 	 */
> 	if (xfeature == XFEATURE_CET_USER ||
> 	    xfeature == XFEATURE_CET_KERNEL)
> 		ret |= boot_cpu_has(X86_FEATURE_IBT)
> 		
> 	return ret;
> }
> 
> See how that's extensible?  You can add as many special cases as you want.
> 

Yes.

Thanks,
Yu-cheng