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Date: Mon, 30 Nov 2020 16:23:29 +0800
From: Zong Li <zong.li@...ive.com>
To: paul.walmsley@...ive.com, palmer@...belt.com, sboyd@...nel.org,
schwab@...ux-m68k.org, pragnesh.patel@...nfive.com,
aou@...s.berkeley.edu, mturquette@...libre.com,
yash.shah@...ive.com, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-riscv@...ts.infradead.org
Cc: Zong Li <zong.li@...ive.com>,
Pragnesh Patel <pragnesh.patel@...ive.com>
Subject: [PATCH v5 4/5] clk: sifive: Fix the wrong bit field shift
The clk enable bit should be 31 instead of 24.
Signed-off-by: Zong Li <zong.li@...ive.com>
Reported-by: Pragnesh Patel <pragnesh.patel@...ive.com>
---
drivers/clk/sifive/sifive-prci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index 7e509dfb72d1..88493f3b9edf 100644
--- a/drivers/clk/sifive/sifive-prci.h
+++ b/drivers/clk/sifive/sifive-prci.h
@@ -59,7 +59,7 @@
/* DDRPLLCFG1 */
#define PRCI_DDRPLLCFG1_OFFSET 0x10
-#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
+#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
/* GEMGXLPLLCFG0 */
@@ -81,7 +81,7 @@
/* GEMGXLPLLCFG1 */
#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
-#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
+#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
/* CORECLKSEL */
--
2.29.2
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