linux-kernel - Re: [PATCH] PCI: aardvark: Update comment about disabling link training

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20201130105200.GA16758@e121166-lin.cambridge.arm.com>
Date:   Mon, 30 Nov 2020 10:52:00 +0000
From:   Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To:     Pali Rohár <pali@...nel.org>
Cc:     Bjorn Helgaas <helgaas@...nel.org>, Rob Herring <robh@...nel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] PCI: aardvark: Update comment about disabling link
 training

On Mon, Nov 30, 2020 at 12:17:41AM +0100, Pali Rohár wrote:
> On Sunday 11 October 2020 19:21:49 Pali Rohár wrote:
> > On Thursday 24 September 2020 17:22:32 Pali Rohár wrote:
> > > On Thursday 24 September 2020 10:11:06 Bjorn Helgaas wrote:
> > > > On Thu, Sep 24, 2020 at 10:46:18AM +0200, Pali Rohár wrote:
> > > > > It is not HW bug or workaround for some cards but it is requirement by PCI
> > > > > Express spec. After fundamental reset is needed 100ms delay prior enabling
> > > > > link training. So update comment in code to reflect this requirement.
> > > > > 
> > > > > Signed-off-by: Pali Rohár <pali@...nel.org>
> > > > > ---
> > > > >  drivers/pci/controller/pci-aardvark.c | 7 ++++++-
> > > > >  1 file changed, 6 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> > > > > index 50ab6d7519ae..19b9b79226e5 100644
> > > > > --- a/drivers/pci/controller/pci-aardvark.c
> > > > > +++ b/drivers/pci/controller/pci-aardvark.c
> > > > > @@ -259,7 +259,12 @@ static void advk_pcie_issue_perst(struct advk_pcie *pcie)
> > > > >  	if (!pcie->reset_gpio)
> > > > >  		return;
> > > > >  
> > > > > -	/* PERST does not work for some cards when link training is enabled */
> > > > > +	/*
> > > > > +	 * As required by PCI Express spec a delay for at least 100ms after
> > > > > +	 * de-asserting PERST# signal is needed before link training is enabled.
> > > > > +	 * So ensure that link training is disabled prior de-asserting PERST#
> > > > > +	 * signal to fulfill that PCI Express spec requirement.
> > > > 
> > > > Can you please include the spec citation here?  In the PCIe base spec,
> > > > PERST# is only mentioned in PCIe r5.0, sec 6.6.1, and I don't see the
> > > > connection there to 100ms between de-assert of PERST# and enabling
> > > > link training.
> > > 
> > > Hello! I copied this "comment" from other place in pci-aardvark.c where
> > > that timeout 100ms is already applied. Timeout with explanation comment
> > > was introduced in following commit:
> > > 
> > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f4c7d053d7f7
> > > 
> > > Here are links to discussions about that patch:
> > > 
> > > https://lore.kernel.org/linux-pci/20190313213752.1246-1-repk@triplefau.lt/T/#u
> > > https://lore.kernel.org/linux-pci/20190522213351.21366-2-repk@triplefau.lt/T/#u
> > 
> > Bjorn or Lorenzo, do you need something else for this patch? It just
> > updates comment and basically clarify why PERST does not work for some
> > cards when link training is enabled.
> 
> PING?

Apologies, I marked it as "changes requested" following Bjorn's reply.
Would you mind please adding a link to the relevant PCI specs in the
comment ?

I understood you copied the comment, it is worth adding that link to all
of them if you don't mind, it can be a preparation patch if you wish.

Thanks,
Lorenzo

> > > > Sec 6.1.1 does talk about 100ms before sending config requests (for
> > > > ports that support <= 5 GT/s), and 100ms after link training completes
> > > > (for ports that support > 5 GT/s).
> > > > 
> > > > Maybe there's more language in a form-factor spec or something?
> > > > 
> > > > > +	 */
> > > > >  	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
> > > > >  	reg &= ~LINK_TRAINING_EN;
> > > > >  	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
> > > > > -- 
> > > > > 2.20.1
> > > > >