linux-kernel - Re: [PATCH 5/6] arm64: dts: qcom: sm8250: add mi2s pinconfs

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Date:   Tue, 1 Dec 2020 13:19:22 -0600
From:   Bjorn Andersson <bjorn.andersson@...aro.org>
To:     Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Cc:     linux-arm-msm@...r.kernel.org, agross@...nel.org,
        robh+dt@...nel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5/6] arm64: dts: qcom: sm8250: add mi2s pinconfs

On Tue 01 Dec 09:37 CST 2020, Srinivas Kandagatla wrote:

> Add primary and tertinary mi2s pinconfs required to get I2S audio.
> 
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8250.dtsi | 98 ++++++++++++++++++++++++++++
>  1 file changed, 98 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 19dd7460e586..a87940e157be 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -1561,6 +1561,9 @@
>  			};
>  		};
>  
> +		sound: sound {
> +		};
> +
>  		usb_1_hsphy: phy@...3000 {
>  			compatible = "qcom,sm8250-usb-hs-phy",
>  				     "qcom,usb-snps-hs-7nm-phy";
> @@ -1884,6 +1887,60 @@
>  			gpio-ranges = <&tlmm 0 0 180>;
>  			wakeup-parent = <&pdc>;
>  
> +			pri_mi2s_sck_active: pri-mi2s-sck-active {
> +				mux {

As in patch 3, please make these state-centric and flatten the inner
subnode.

> +					pins = "gpio138";
> +					function = "mi2s0_sck";
> +				};
> +
> +				config {
> +					pins = "gpio138";
> +					drive-strength = <8>;
> +					bias-disable;
> +					output-high;

If function is mi2s0_sck is the output value relevant? Or should this
be dropped?

Regards,
Bjorn

> +				};
> +			};
> +
> +			pri_mi2s_ws_active: pri-mi2s-ws-active {
> +				mux {
> +					pins = "gpio141";
> +					function = "mi2s0_ws";
> +				};
> +
> +				config {
> +					pins = "gpio141";
> +					drive-strength = <8>;
> +					output-high;
> +				};
> +			};
> +
> +			pri_mi2s_sd0_active: pri-mi2s-sd0-active {
> +				mux {
> +					pins = "gpio139";
> +					function = "mi2s0_data0";
> +				};
> +
> +				config {
> +					pins = "gpio139";
> +					drive-strength = <8>;
> +					bias-disable;
> +					output-high;
> +				};
> +			};
> +
> +			pri_mi2s_sd1_active: pri-mi2s-sd1-active {
> +				mux {
> +					pins = "gpio140";
> +					function = "mi2s0_data1";
> +				};
> +
> +				config {
> +					pins = "gpio140";
> +					drive-strength = <8>;
> +					output-high;
> +				};
> +			};
> +
>  			qup_i2c0_default: qup-i2c0-default {
>  				mux {
>  					pins = "gpio28", "gpio29";
> @@ -2480,6 +2537,47 @@
>  					function = "qup18";
>  				};
>  			};
> +
> +			tert_mi2s_sck_active: tert-mi2s-sck-active {
> +				mux {
> +					pins = "gpio133";
> +					function = "mi2s2_sck";
> +				};
> +
> +				config {
> +					pins = "gpio133";
> +					drive-strength = <8>;
> +					bias-disable;
> +					output-high;
> +				};
> +			};
> +
> +			tert_mi2s_sd0_active: tert-mi2s-sd0-active {
> +				mux {
> +					pins = "gpio134";
> +					function = "mi2s2_data0";
> +				};
> +
> +				config {
> +					pins = "gpio134";
> +					drive-strength = <8>;
> +					bias-disable;
> +					output-high;
> +				};
> +			};
> +
> +			tert_mi2s_ws_active: tert-mi2s-ws-active {
> +				mux {
> +					pins = "gpio135";
> +					function = "mi2s2_ws";
> +				};
> +
> +				config {
> +					pins = "gpio135";
> +					drive-strength = <8>;
> +					output-high;
> +				};
> +			};
>  		};
>  
>  		apps_smmu: iommu@...00000 {
> -- 
> 2.21.0
>