linux-kernel - Re: [PATCH 03/22] keembay-ipc: Add Keem Bay IPC module

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Message-ID: <X8fkflUXwSTGAoyQ@kroah.com>
Date:   Wed, 2 Dec 2020 20:01:18 +0100
From:   Greg KH <gregkh@...uxfoundation.org>
To:     mark gross <mgross@...ux.intel.com>
Cc:     markgross@...nel.org, arnd@...db.de, bp@...e.de,
        damien.lemoal@....com, dragan.cvetic@...inx.com, corbet@....net,
        leonard.crestez@....com, palmerdabbelt@...gle.com,
        paul.walmsley@...ive.com, peng.fan@....com, robh+dt@...nel.org,
        shawnguo@...nel.org, linux-kernel@...r.kernel.org,
        Daniele Alessandrelli <daniele.alessandrelli@...el.com>
Subject: Re: [PATCH 03/22] keembay-ipc: Add Keem Bay IPC module

On Wed, Dec 02, 2020 at 09:42:00AM -0800, mark gross wrote:
> On Wed, Dec 02, 2020 at 07:16:20AM +0100, Greg KH wrote:
> > On Tue, Dec 01, 2020 at 02:34:52PM -0800, mgross@...ux.intel.com wrote:
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -8955,6 +8955,14 @@ M:	Deepak Saxena <dsaxena@...xity.net>
> > >  S:	Maintained
> > >  F:	drivers/char/hw_random/ixp4xx-rng.c
> > >  
> > > +INTEL KEEM BAY IPC DRIVER
> > > +M:	Daniele Alessandrelli <daniele.alessandrelli@...el.com>
> > > +M:	Mark Gross <mgross@...ux.intel.com>
> > > +S:	Maintained
> > > +F:	Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml
> > > +F:	drivers/soc/intel/keembay-ipc.c
> > > +F:	include/linux/soc/intel/keembay-ipc.h
> > 
> > Sad that Intel is not going to actually pay you all to do this
> > maintenance work for a brand new subsystem you are wanting to add to the
> > tree :(
> I thought adding my name to these maintainer items would help with continuity
> as the individual engineers tend to move on to other things over time.
> 
> While I'm paid for a number of things at intel this is one of them.  My role is
> as stable as I choose it to be at the point I'm at in my Intel career and the
> business unit I'm now part of.  We can leave my name off if that would be
> better.
> 
> Even if I'm not a VPU IP domain expert like Daniele is I can still chase down
> the experts as needed after Daniele grows into other things over time.

I'm not objecting to your, or anyone else's name on this at all.  I'm
just asking about Intel's support for this new codebase being added.
Having a new subsystem from a major company and not have someone paid to
actually maintain it seems really odd to me.

That's all.  If that's Intel's stance, that's fine, just wanted to
clarify it is correct as I know some people at Intel have been confused
recently about just what the S: field means.

thanks,

greg k-h