lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <6543A0E0-2DFE-4620-8C95-046B4785132C@intel.com>
Date:   Wed, 2 Dec 2020 22:54:26 +0000
From:   "Kelley, Sean V" <sean.v.kelley@...el.com>
To:     Bjorn Helgaas <helgaas@...nel.org>
CC:     "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        Jonathan Cameron <Jonathan.Cameron@...wei.com>,
        "xerces.zhao@...il.com" <xerces.zhao@...il.com>,
        "Wysocki, Rafael J" <rafael.j.wysocki@...el.com>,
        "Raj, Ashok" <ashok.raj@...el.com>,
        "Luck, Tony" <tony.luck@...el.com>,
        "Kuppuswamy, Sathyanarayanan" <sathyanarayanan.kuppuswamy@...el.com>,
        "Zhuo, Qiuxu" <qiuxu.zhuo@...el.com>,
        Linux PCI <linux-pci@...r.kernel.org>,
        "Linux Kernel Mailing List" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v12 10/15] PCI/ERR: Limit AER resets in pcie_do_recovery()

Hi Bjorn,


> On Dec 2, 2020, at 1:27 PM, Bjorn Helgaas <helgaas@...nel.org> wrote:
> 
> On Wed, Dec 02, 2020 at 08:53:54PM +0000, Kelley, Sean V wrote:
>>> On Nov 30, 2020, at 4:25 PM, Bjorn Helgaas <helgaas@...nel.org> wrote:
>>> On Mon, Nov 30, 2020 at 07:54:37PM +0000, Kelley, Sean V wrote:
> 
>>>> -	if (pcie_aer_is_native(bridge))
>>>> -		pcie_clear_device_status(bridge);
>>>> -	pci_aer_clear_nonfatal_status(bridge);
>>>> 
>>>> +	if (type == PCI_EXP_TYPE_ROOT_PORT ||
>>>> +	    type == PCI_EXP_TYPE_DOWNSTREAM ||
>>>> +	    type == PCI_EXP_TYPE_RC_EC) {
>>>> +		if (pcie_aer_is_native(bridge))
>>>> +			pcie_clear_device_status(bridge);
>>>> +		pci_aer_clear_nonfatal_status(bridge);
>>>> +	}
> 
> Back to this specific hunk, what if we made it this?
> 
>  struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
> 
>  if (host->native_aer || pcie_ports_native) {
>    pcie_clear_device_status(bridge);
>    pci_aer_clear_nonfatal_status(bridge);
>  }
> 
> Previously, if "bridge" didn't have an AER Capability, we didn't
> pcie_clear_device_status().  In the case of a DPC bridge without AER,
> I think we *should* call pcie_clear_device_status().

Agree, I was overlooking DPC here with the AER check.

> 
> Otherwise, I think this should work the same and would be a little
> simpler.

Looks fine to me.  It simplifies it a bit.

> 
>>> It seems like there are basically two devices of interest in
>>> pcie_do_recovery(): the endpoint where we have to call the driver
>>> error recovery, and the port that generated the interrupt.  I wonder
>>> if this would make more sense if the caller passed both of them in
>>> explicitly instead of having pcie_do_recovery() check the type of
>>> "dev" and try to figure things out after the fact.
>> 
>> On this last point I wanted to add that this is a possibility that
>> could provide a clearer distinction, especially where actions need
>> to be taken or not taken as a part of pcie_do_recovery(), i.e.,
>> bridge versus dev.  In this patch series we have taken steps to
>> minimize the need for the distinction by pushing the awareness into
>> the driver’s error recovery routine, i.e., dev->rcec.  A future
>> evolution after this series could lead to both devices of interest
>> being passed explicitly for the larger scope EDR/DPC/AER/etc.
> 
> Yeah, not worth doing in *this* series.
> 
> Bjorn

Thanks,

Sean

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ