linux-kernel - Re: [PATCH v2 1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support

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Message-ID: <CACPK8XfySi5=r4e__djHg-LtFqhV7j+-Pp+t4zevro=KK0eBig@mail.gmail.com>
Date:   Wed, 2 Dec 2020 06:40:47 +0000
From:   Joel Stanley <joel@....id.au>
To:     Troy Lee <troy_lee@...eedtech.com>
Cc:     Stefan Schaeckeler <sschaeck@...co.com>,
        Rob Herring <robh+dt@...nel.org>,
        Andrew Jeffery <andrew@...id.au>,
        Borislav Petkov <bp@...en8.de>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Tony Luck <tony.luck@...el.com>,
        James Morse <james.morse@....com>,
        Robert Richter <rrichter@...vell.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:ARM/ASPEED MACHINE SUPPORT" 
        <linux-arm-kernel@...ts.infradead.org>,
        "moderated list:ARM/ASPEED MACHINE SUPPORT" 
        <linux-aspeed@...ts.ozlabs.org>,
        open list <linux-kernel@...r.kernel.org>,
        "open list:EDAC-CORE" <linux-edac@...r.kernel.org>,
        leetroy@...il.com, Ryan Chen <ryan_chen@...eedtech.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: edac: aspeed-sdram-edac: Add
 ast2400/ast2600 support

On Wed, 2 Dec 2020 at 06:37, Troy Lee <troy_lee@...eedtech.com> wrote:
>
> Adding Aspeed AST2400 and AST2600 binding for edac driver.
>
> Signed-off-by: Troy Lee <troy_lee@...eedtech.com>

Acked-by: Joel Stanley <joel@....id.au>

> ---
>  .../devicetree/bindings/edac/aspeed-sdram-edac.txt       | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> index 6a0f3d90d682..8ca9e0a049d8 100644
> --- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> @@ -1,6 +1,6 @@
> -Aspeed AST2500 SoC EDAC node
> +Aspeed BMC SoC EDAC node
>
> -The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
> +The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
>  correction check).
>
>  The memory controller supports SECDED (single bit error correction, double bit
> @@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory controller.
>
>
>  Required properties:
> -- compatible: should be "aspeed,ast2500-sdram-edac"
> +- compatible: should be one of
> +       - "aspeed,ast2400-sdram-edac"
> +       - "aspeed,ast2500-sdram-edac"
> +       - "aspeed,ast2600-sdram-edac"
>  - reg:        sdram controller register set should be <0x1e6e0000 0x174>
>  - interrupts: should be AVIC interrupt #0
>
> --
> 2.17.1
>