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Message-ID: <X8escb4SZXEpiR0n@aptenodytes>
Date:   Wed, 2 Dec 2020 16:02:09 +0100
From:   Paul Kocialkowski <paul.kocialkowski@...tlin.com>
To:     Maxime Ripard <maxime@...no.tech>
Cc:     linux-media@...r.kernel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-doc@...r.kernel.org, devel@...verdev.osuosl.org,
        linux-sunxi@...glegroups.com, Yong Deng <yong.deng@...ewell.com>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Rob Herring <robh+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...l.net>,
        Jonathan Corbet <corbet@....net>,
        Kishon Vijay Abraham I <kishon@...com>,
        Vinod Koul <vkoul@...nel.org>,
        Helen Koike <helen.koike@...labora.com>,
        Dafna Hirschfeld <dafna.hirschfeld@...labora.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Sakari Ailus <sakari.ailus@...ux.intel.com>,
        Hans Verkuil <hans.verkuil@...co.com>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        kevin.lhopital@...mail.com
Subject: Re: [PATCH v2 09/19] ARM: dts: sunxi: h3/h5: Add CSI controller port
 for parallel input

Hi,

On Tue 01 Dec 20, 13:14, Maxime Ripard wrote:
> On Sat, Nov 28, 2020 at 03:28:29PM +0100, Paul Kocialkowski wrote:
> > Since the CSI controller binding is getting a bit more complex due
> > to the addition of MIPI CSI-2 bridge support, make the ports node
> > explicit with the parallel port.
> > 
> > This way, it's clear that the controller only supports parallel
> > interface input and there's no confusion about the port number.
> > 
> > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
> > ---
> >  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > index 9be13378d4df..02b698cace6a 100644
> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > @@ -803,6 +803,15 @@ csi: camera@...0000 {
> >  			pinctrl-names = "default";
> >  			pinctrl-0 = <&csi_pins>;
> >  			status = "disabled";
> > +
> > +			ports {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				csi_in_parallel: port@0 {
> > +					reg = <0>;
> > +				};
> > +			};
> >  		};
> 
> This will create a DTC warning, since port@0 is the only node, and is
> equivalent to port

I'm not seeing the warning when running dtbs_check.
More generally, why is it a problem that there's only one node defined?

One issue that I did see is that the port node doesn't have an endpoint
here, so I will remove the requirement to have an endpoint in the bindings
documentation to allow this kind of definition.

Cheers,

Paul

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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