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Message-ID: <alpine.GSO.2.00.2012031617500.7044@dmz.c-home.cz>
Date: Thu, 3 Dec 2020 17:25:21 +0100 (CET)
From: Martin Cerveny <martin@...ome.cz>
To: Chen-Yu Tsai <wens@...e.org>
cc: Martin Cerveny <m.cerveny@...puter.org>,
Maxime Ripard <mripard@...nel.org>, devel@...verdev.osuosl.org,
devicetree <devicetree@...r.kernel.org>,
Jernej Skrabec <jernej.skrabec@...l.net>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Rob Herring <robh+dt@...nel.org>,
Paul Kocialkowski <paul.kocialkowski@...tlin.com>,
Mark Brown <broonie@...nel.org>,
Linux Media Mailing List <linux-media@...r.kernel.org>,
Lee Jones <lee.jones@...aro.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
Icenowy Zheng <icenowy@...c.io>
Subject: Re: [PATCH v3 3/6] ARM: dts: sun8i: v3s: Add node for system
control
Hello.
On Thu, 3 Dec 2020, Chen-Yu Tsai wrote:
> Hi,
>
> On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny <m.cerveny@...puter.org> wrote:
>>
>> Allwinner V3s has system control and SRAM C1 region similar to H3.
>>
>> Signed-off-by: Martin Cerveny <m.cerveny@...puter.org>
>> ---
>> arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
>> index 0c7341676921..70193512c222 100644
>> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
>> @@ -161,6 +161,20 @@ syscon: system-control@...0000 {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> ranges;
>> +
>> + sram_c: sram@...0000 {
>> + compatible = "mmio-sram";
>> + reg = <0x01d00000 0x80000>;
>
> How was this address derived? Did you check that there is actually SRAM here?
Yes, I did some checking (mmap). But I repeated measurement and found
mirrored regions:
- SRAM_C is mirrored from 0x0000_4000 (primary location) to 0x01d0_4000 (size 0xb000)
(probably exact size is 0xb0c0)
- rest of 0x01d0_0000 are discontinuously filled with R/W register sets
(probably some internals registers from VE) that I thought to be SRAM too
- register SRAM_CTRL_REG0==0x01c00_0000 (value 0x7fff_ffff) switch whole
region 0x01d0_0000-0x01df_ffff __AND__ 0x0000_4000-0x0000_ffff
- VE/cedrus code use this regions indirectly
(VE_AVC_SRAM_PORT_OFFSET/VE_AVC_SRAM_PORT_DATA...)
and it is not influenced by "true" SRAM mapping or size
-> so I suppose to better use only SRAM_C lower definition:
---
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index e8f304125e2d..90d703e5b73b 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -162,17 +162,17 @@ syscon: system-control@...0000 {
#size-cells = <1>;
ranges;
- sram_c: sram@...0000 {
+ sram_c: sram@...0 {
compatible = "mmio-sram";
- reg = <0x01d00000 0x80000>;
+ reg = <0x4000 0xb000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x01d00000 0x80000>;
+ ranges = <0 0 0x4000 0xb000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun8i-v3s-sram-c1",
"allwinner,sun4i-a10-sram-c1";
- reg = <0x000000 0x80000>;
+ reg = <0x0 0xb000>;
};
};
};
---
Does someone have accessible specific documentation of VE/cedrus for V3s ?
Regards, Martin
> ChenYu
>
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x01d00000 0x80000>;
>> +
>> + ve_sram: sram-section@0 {
>> + compatible = "allwinner,sun8i-v3s-sram-c1",
>> + "allwinner,sun4i-a10-sram-c1";
>> + reg = <0x000000 0x80000>;
>> + };
>> + };
>> };
>>
>> tcon0: lcd-controller@...c000 {
>> --
>> 2.25.1
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@...ts.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
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