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Message-ID: <CAEExFWs0aXNuQyazdfgeFkjrj9cBbY0vZMSgNHRPkf_XCLhJbw@mail.gmail.com>
Date: Sat, 5 Dec 2020 22:44:43 +0800
From: Frank Lee <tiny.windzz@...il.com>
To: Shuosheng Huang <huangshuosheng@...winnertech.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Maxime Ripard <mripard@...nel.org>,
Chen-Yu Tsai <wens@...e.org>, jernej.skrabec@...l.net,
devicetree <devicetree@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] arm64: dts: allwinner: a100: Add CPU Operating
Performance Points table
HI shuosheng,
On Fri, Dec 4, 2020 at 3:11 PM Shuosheng Huang
<huangshuosheng@...winnertech.com> wrote:
>
> Add an Operating Performance Points table for the CPU cores to
> enable Dynamic Voltage & Frequency Scaling on the A100.
>
> Signed-off-by: Shuosheng Huang <huangshuosheng@...winnertech.com>
> ---
> .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++
> .../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90 +++++++++++++++++++
> .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++
> 3 files changed, 103 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> index d34c2bb1079f..7c579923f973 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> @@ -6,6 +6,7 @@
> /dts-v1/;
>
> #include "sun50i-a100.dtsi"
> +#include "sun50i-a100-cpu-opp.dtsi"
>
> /{
> model = "Allwinner A100 Perf1";
> @@ -20,6 +21,10 @@ chosen {
> };
> };
>
> +&cpu0 {
> + cpu-supply = <®_dcdc2>;
> +};
> +
> &pio {
> vcc-pb-supply = <®_dcdc1>;
> vcc-pc-supply = <®_eldo1>;
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> new file mode 100644
> index 000000000000..bc8ceaa38392
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2020 Yangtao Li <frank@...winnertech.com>
> +// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@...winnertech.com>
> +
> +/ {
> + cpu_opp_table: cpu-opp-table {
> + compatible = "allwinner,sun50i-h6-operating-points";
> + nvmem-cells = <&cpu_speed_grade>;
> + opp-shared;
> +
> + opp@...000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <408000000>;
> +
> + opp-microvolt-speed0 = <900000 900000 1200000>;
> + opp-microvolt-speed0 = <900000 900000 1200000>;
> + opp-microvolt-speed0 = <900000 900000 1200000>;
> + };
This should be opp-microvolt-speed0, opp-microvolt-speed1 and
opp-microvolt-speed2.
You may have problems with the replacement when forming the patch.
The following also needs to be modified.
Yangtao
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