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Date:   Sat, 5 Dec 2020 12:15:25 +0800
From:   Yongqiang Niu <yongqiang.niu@...iatek.com>
To:     Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        CK Hu <ck.hu@...iatek.com>
CC:     Jassi Brar <jassisinghbrar@...il.com>,
        Bibby Hsieh <bibby.hsieh@...iatek.com>,
        Yongqiang Niu <yongqiang.niu@...iatek.com>,
        Dennis YC Hsieh <dennis-yc.hsieh@...iatek.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
Subject: [PATCH v1, 2/5] arm64: dts: mt8192: add gce node

add gce node

Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 69d45c7..7c0c233 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -272,6 +273,16 @@
 			clock-names = "clk13m";
 		};
 
+		gce: mailbox@...28000 {
+			compatible = "mediatek,mt8192-gce";
+			reg = <0 0x10228000 0 0x4000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <3>;
+			clocks = <&infracfg CLK_INFRA_GCE>,
+				 <&infracfg CLK_INFRA_GCE_26M>;
+			clock-names = "gce", "gce-timer";
+		};
+
 		scp_adsp: syscon@...20000 {
 			compatible = "mediatek,mt8192-scp_adsp", "syscon";
 			reg = <0 0x10720000 0 0x1000>;
-- 
1.8.1.1.dirty

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