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Message-ID: <2128b898-ee5f-fd71-77af-4a3d957088a5@gmail.com>
Date: Tue, 8 Dec 2020 01:11:18 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>,
Mikko Perttunen <cyndis@...si.fi>,
Nicolas Chauvet <kwizart@...il.com>,
Georgi Djakov <georgi.djakov@...aro.org>,
Peter Geis <pgwipeout@...il.com>,
MyungJoo Ham <myungjoo.ham@...sung.com>,
Viresh Kumar <vireshk@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Michael Turquette <mturquette@...libre.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Jonathan Hunter <jonathanh@...dia.com>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Chanwoo Choi <cw00.choi@...sung.com>
Cc: linux-tegra@...r.kernel.org, devicetree@...r.kernel.org,
dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org
Subject: Re: [PATCH v11 00/10] Introduce memory interconnect for NVIDIA Tegra
SoCs
05.12.2020 17:09, Krzysztof Kozlowski пишет:
> On Thu, 3 Dec 2020 22:24:29 +0300, Dmitry Osipenko wrote:
>> This series brings initial support for memory interconnect to Tegra20,
>> Tegra30 and Tegra124 SoCs.
>>
>> For the starter only display controllers and devfreq devices are getting
>> interconnect API support, others could be supported later on. The display
>> controllers have the biggest demand for interconnect API right now because
>> dynamic memory frequency scaling can't be done safely without taking into
>> account bandwidth requirement from the displays. In particular this series
>> fixes distorted display output on T30 Ouya and T124 TK1 devices.
>>
>> [...]
>
> Applied, thanks!
>
> [01/10] dt-bindings: memory: tegra20: emc: Document opp-supported-hw property
> [02/10] memory: tegra20: Support hardware versioning and clean up OPP table initialization
> [03/10] memory: tegra30: Support interconnect framework
> commit: 01a51facb74fb337ff9fe734caa85dd6e246ef48
>
> Best regards,
>
Awesome, thanks! Good to have the warning splat silenced.
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