linux-kernel - Re: [PATCH] arm64: mm: decrease the section size to reduce the memory reserved for the page map

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAMj1kXGQ-CeYcbS-hc+Yy8DKHm2t-RYsLu4+7wOG1bWuJqkjGQ@mail.gmail.com>
Date:   Mon, 7 Dec 2020 10:09:06 +0100
From:   Ard Biesheuvel <ardb@...nel.org>
To:     Will Deacon <will@...nel.org>, Marc Zyngier <maz@...nel.org>
Cc:     Wei Li <liwei213@...wei.com>,
        Barry Song <song.bao.hua@...ilicon.com>,
        Steve Capper <steve.capper@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Mike Rapoport <rppt@...ux.ibm.com>, fengbaopeng2@...ilicon.com,
        butao@...ilicon.com,
        Nicolas Saenz Julienne <nsaenzjulienne@...e.de>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] arm64: mm: decrease the section size to reduce the memory
 reserved for the page map

(+ Marc)

On Fri, 4 Dec 2020 at 12:14, Will Deacon <will@...nel.org> wrote:
>
> On Fri, Dec 04, 2020 at 09:44:43AM +0800, Wei Li wrote:
> > For the memory hole, sparse memory model that define SPARSEMEM_VMEMMAP
> > do not free the reserved memory for the page map, decrease the section
> > size can reduce the waste of reserved memory.
> >
> > Signed-off-by: Wei Li <liwei213@...wei.com>
> > Signed-off-by: Baopeng Feng <fengbaopeng2@...ilicon.com>
> > Signed-off-by: Xia Qing <saberlily.xia@...ilicon.com>
> > ---
> >  arch/arm64/include/asm/sparsemem.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/include/asm/sparsemem.h b/arch/arm64/include/asm/sparsemem.h
> > index 1f43fcc79738..8963bd3def28 100644
> > --- a/arch/arm64/include/asm/sparsemem.h
> > +++ b/arch/arm64/include/asm/sparsemem.h
> > @@ -7,7 +7,7 @@
> >
> >  #ifdef CONFIG_SPARSEMEM
> >  #define MAX_PHYSMEM_BITS     CONFIG_ARM64_PA_BITS
> > -#define SECTION_SIZE_BITS    30
> > +#define SECTION_SIZE_BITS    27
>
> We chose '30' to avoid running out of bits in the page flags. What changed?
>
> With this patch, I can trigger:
>
> ./include/linux/mmzone.h:1170:2: error: Allocator MAX_ORDER exceeds SECTION_SIZE
> #error Allocator MAX_ORDER exceeds SECTION_SIZE
>
> if I bump up NR_CPUS and NODES_SHIFT.
>

Does this mean we will run into problems with the GICv3 ITS LPI tables
again if we are forced to reduce MAX_ORDER to fit inside
SECTION_SIZE_BITS?