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Message-Id: <20201207091827.31529-1-huangshuosheng@allwinnertech.com>
Date: Mon, 7 Dec 2020 17:18:27 +0800
From: Shuosheng Huang <huangshuosheng@...winnertech.com>
To: tiny.windzz@...il.com, rjw@...ysocki.net, viresh.kumar@...aro.org,
mripard@...nel.org, wens@...e.org, jernej.skrabec@...l.net
Cc: linux-pm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Shuosheng Huang <huangshuosheng@...winnertech.com>
Subject: [PATCH V2 2/3] cpufreq: sun50i: add a100 cpufreq support
Add cpufreq nvmem based for allwinner a100 SoC, it's similar to h6.
Signed-off-by: Shuosheng Huang <huangshuosheng@...winnertech.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/sun50i-cpufreq-nvmem.c | 32 ++++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 3776d960f405..2ebf5d9cb616 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -102,6 +102,7 @@ static const struct of_device_id whitelist[] __initconst = {
*/
static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "allwinner,sun50i-h6", },
+ { .compatible = "allwinner,sun50i-a100", },
{ .compatible = "calxeda,highbank", },
{ .compatible = "calxeda,ecx-2000", },
diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
index da23d581a4b4..def4a19abe16 100644
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -25,6 +25,9 @@
#define SUN50I_H6_NVMEM_MASK 0x7
#define SUN50I_H6_NVMEM_SHIFT 5
+#define SUN50I_A100_NVMEM_MASK 0xf
+#define SUN50I_A100_NVMEM_SHIFT 12
+
struct sunxi_cpufreq_soc_data {
u32 (*efuse_xlate)(void *efuse);
};
@@ -55,6 +58,30 @@ static u32 sun50i_h6_efuse_xlate(struct nvmem_cell *speedbin_nvmem)
return 0;
}
+static u32 sun50i_a100_efuse_xlate(struct nvmem_cell *speedbin_nvmem)
+{
+ size_t len;
+ u32 *speedbin;
+ u32 efuse_value;
+
+ speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+ if (IS_ERR(speedbin))
+ return PTR_ERR(speedbin);
+
+ efuse_value = (*(u16 *)efuse >> SUN50I_A100_NVMEM_SHIFT) &
+ SUN50I_A100_NVMEM_MASK;
+ kfree(speedbin);
+
+ switch (efuse_value) {
+ case 0b100:
+ return 2;
+ case 0b010:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
/**
* sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
* @soc_data: pointer to sunxi_cpufreq_soc_data context
@@ -188,8 +215,13 @@ static const struct sunxi_cpufreq_soc_data sun50i_h6_data = {
.efuse_xlate = sun50i_h6_efuse_xlate,
};
+static const struct sunxi_cpufreq_soc_data sun50i_a100_data = {
+ .efuse_xlate = sun50i_a100_efuse_xlate,
+};
+
static const struct of_device_id sun50i_cpufreq_match_list[] = {
{ .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data },
+ { .compatible = "allwinner,sun50i-a100", .data = &sun50i_a100_data },
{}
};
--
2.28.0
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