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Message-ID: <20201207102002.GA3825@willie-the-truck>
Date: Mon, 7 Dec 2020 10:20:03 +0000
From: Will Deacon <will@...nel.org>
To: Quentin Perret <qperret@...gle.com>
Cc: Fuad Tabba <tabba@...gle.com>,
Catalin Marinas <catalin.marinas@....com>,
Marc Zyngier <maz@...nel.org>,
James Morse <james.morse@....com>,
Julien Thierry <julien.thierry.kdev@...il.com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Rob Herring <robh+dt@...nel.org>,
Frank Rowand <frowand.list@...il.com>,
"moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)"
<linux-arm-kernel@...ts.infradead.org>,
open list <linux-kernel@...r.kernel.org>,
"open list:KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)"
<kvmarm@...ts.cs.columbia.edu>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE"
<devicetree@...r.kernel.org>, kernel-team@...roid.com,
Android KVM <android-kvm@...gle.com>
Subject: Re: [RFC PATCH 16/27] KVM: arm64: Prepare Hyp memory protection
On Fri, Dec 04, 2020 at 06:01:52PM +0000, Quentin Perret wrote:
> On Thursday 03 Dec 2020 at 12:57:33 (+0000), Fuad Tabba wrote:
> <snip>
> > > +int hyp_create_idmap(void);
> > > +int hyp_map_vectors(void);
> > > +int hyp_back_vmemmap(phys_addr_t phys, unsigned long size, phys_addr_t back);
> > > +int hyp_cpu_set_vector(enum arm64_hyp_spectre_vector slot);
> > > +int hyp_create_mappings(void *from, void *to, enum kvm_pgtable_prot prot);
> > > +int __hyp_create_mappings(unsigned long start, unsigned long size,
> > > + unsigned long phys, unsigned long prot);
> > > +unsigned long __hyp_create_private_mapping(phys_addr_t phys, size_t size,
> > > + unsigned long prot);
> > > +
> >
> > nit: I also thought that the hyp_create_mappings function names are a
> > bit confusing, since there's the create_hyp_mappings functions which
> > use the aforementioned *hyp_pgtable.
>
> Sure, happy to re-name those (and hyp_pgtable above). Any suggestions?
>
>
> <snip>
> > > +SYM_FUNC_START(__kvm_init_switch_pgd)
> > > + /* Turn the MMU off */
> > > + pre_disable_mmu_workaround
> > > + mrs x2, sctlr_el2
> > > + bic x3, x2, #SCTLR_ELx_M
> > > + msr sctlr_el2, x3
> > > + isb
> > > +
> > > + tlbi alle2
> > > +
> > > + /* Install the new pgtables */
> > > + ldr x3, [x0, #NVHE_INIT_PGD_PA]
> > > + phys_to_ttbr x4, x3
> > > +alternative_if ARM64_HAS_CNP
> > > + orr x4, x4, #TTBR_CNP_BIT
> > > +alternative_else_nop_endif
> > > + msr ttbr0_el2, x4
> > > +
> > > + /* Set the new stack pointer */
> > > + ldr x0, [x0, #NVHE_INIT_STACK_HYP_VA]
> > > + mov sp, x0
> > > +
> > > + /* And turn the MMU back on! */
> > > + dsb nsh
> > > + isb
> > > + msr sctlr_el2, x2
> > > + isb
> > > + ret x1
> > > +SYM_FUNC_END(__kvm_init_switch_pgd)
> > > +
> >
> > Should the instruction cache be flushed here (ic iallu), to discard
> > speculatively fetched instructions?
>
> Hmm, Will? Thoughts?
The I-cache is physically tagged, so not sure what invalidation would
achieve here. Fuad -- what do you think could go wrong specifically?
Will
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