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Message-Id: <1607403341-57214-2-git-send-email-yash.shah@sifive.com>
Date: Tue, 8 Dec 2020 10:25:33 +0530
From: Yash Shah <yash.shah@...ive.com>
To: linux-spi@...r.kernel.org, linux-serial@...r.kernel.org,
linux-pwm@...r.kernel.org, linux-i2c@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
devicetree@...r.kernel.org, linux-gpio@...r.kernel.org
Cc: broonie@...nel.org, gregkh@...uxfoundation.org,
aou@...s.berkeley.edu, lee.jones@...aro.org,
u.kleine-koenig@...gutronix.de, thierry.reding@...il.com,
andrew@...n.ch, peter@...sgaard.com, paul.walmsley@...ive.com,
palmer@...belt.com, robh+dt@...nel.org, bgolaszewski@...libre.com,
linus.walleij@...aro.org, Yash Shah <yash.shah@...ive.com>
Subject: [PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
cores ("harts") that are present on FU740-C000 SoC.
Signed-off-by: Yash Shah <yash.shah@...ive.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6925e0..eb6843f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,11 +28,17 @@ properties:
- items:
- enum:
- sifive,rocket0
+ - sifive,bullet0
- sifive,e5
+ - sifive,e7
- sifive,e51
+ - sifive,e71
- sifive,u54-mc
+ - sifive,u74-mc
- sifive,u54
+ - sifive,u74
- sifive,u5
+ - sifive,u7
- const: riscv
- const: riscv # Simulator only
description:
--
2.7.4
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