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Date: Tue, 8 Dec 2020 15:20:46 +0800
From: Shuosheng Huang <huangshuosheng@...winnertech.com>
To: robh+dt@...nel.org, mripard@...nel.org, wens@...e.org,
jernej.skrabec@...l.net, tiny.windzz@...il.com
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Shuosheng Huang <huangshuosheng@...winnertech.com>
Subject: [PATCH v4 5/6] arm64: dts: allwinner: a100: Add Add CPU Operating Performance Points table
Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the A100.
Signed-off-by: Shuosheng Huang <huangshuosheng@...winnertech.com>
---
.../allwinner/sun50i-a100-allwinner-perf1.dts | 1 +
.../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90 +++++++++++++++++++
2 files changed, 91 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index d34c2bb1079f..301793c72cb7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "sun50i-a100.dtsi"
+#include "sun50i-a100-cpu-opp.dtsi"
/{
model = "Allwinner A100 Perf1";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
new file mode 100644
index 000000000000..e245823d70e8
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2020 Yangtao Li <frank@...winnertech.com>
+// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@...winnertech.com>
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "allwinner,sun50i-h6-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp@...000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <408000000>;
+
+ opp-microvolt-speed0 = <900000 900000 1200000>;
+ opp-microvolt-speed1 = <900000 900000 1200000>;
+ opp-microvolt-speed2 = <900000 900000 1200000>;
+ };
+
+ opp@...000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <600000000>;
+
+ opp-microvolt-speed0 = <900000 900000 1200000>;
+ opp-microvolt-speed1 = <900000 900000 1200000>;
+ opp-microvolt-speed2 = <900000 900000 1200000>;
+ };
+
+ opp@...000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <940000 940000 1200000>;
+ opp-microvolt-speed1 = <900000 900000 1200000>;
+ opp-microvolt-speed2 = <900000 900000 1200000>;
+ };
+
+ opp@...0000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <1020000 1020000 1200000>;
+ opp-microvolt-speed1 = <980000 980000 1200000>;
+ opp-microvolt-speed2 = <950000 950000 1200000>;
+ };
+
+ opp@...0000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1200000000>;
+
+ opp-microvolt-speed0 = <1100000 1100000 1200000>;
+ opp-microvolt-speed1 = <1020000 1020000 1200000>;
+ opp-microvolt-speed2 = <1000000 1000000 1200000>;
+ };
+
+ opp@...0000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1160000 1160000 1200000>;
+ opp-microvolt-speed1 = <1060000 1060000 1200000>;
+ opp-microvolt-speed2 = <1030000 1030000 1200000>;
+ };
+
+ opp@...4000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1464000000>;
+
+ opp-microvolt-speed0 = <1180000 1180000 1200000>;
+ opp-microvolt-speed1 = <1180000 1180000 1200000>;
+ opp-microvolt-speed2 = <1130000 1130000 1200000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
--
2.28.0
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