linux-kernel - Re: [PATCH 3/4] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp

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Message-ID: <20201208090710.GC20575@bogon.m.sigxcpu.org>
Date:   Tue, 8 Dec 2020 10:07:10 +0100
From:   Guido Günther <guido.gunther@...i.sm>
To:     Liu Ying <victor.liu@....com>
Cc:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        dri-devel@...ts.freedesktop.org,
        linux-arm-kernel@...ts.infradead.org, kishon@...com,
        vkoul@...nel.org, robh+dt@...nel.org, a.hajda@...sung.com,
        narmstrong@...libre.com, Laurent.pinchart@...asonboard.com,
        jonas@...boo.se, jernej.skrabec@...l.net, airlied@...ux.ie,
        daniel@...ll.ch, shawnguo@...nel.org, s.hauer@...gutronix.de,
        kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
        robert.chiras@....com, martin.kepplinger@...i.sm
Subject: Re: [PATCH 3/4] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel
 combo PHY support for i.MX8qxp

Hi Liu,
Since we now gain optional properties validation would become even more
useful. Could you look into converting to YAML before adding more
values?
Cheers,
 -- Guido

On Fri, Dec 04, 2020 at 03:33:43PM +0800, Liu Ying wrote:
> Add support for Mixel MIPI DPHY + LVDS PHY combo IP
> as found on Freescale i.MX8qxp SoC.
> 
> Cc: Guido Günther <agx@...xcpu.org>
> Cc: Kishon Vijay Abraham I <kishon@...com>
> Cc: Vinod Koul <vkoul@...nel.org>
> Cc: Rob Herring <robh+dt@...nel.org>
> Cc: NXP Linux Team <linux-imx@....com>
> Signed-off-by: Liu Ying <victor.liu@....com>
> ---
>  Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
> index 9b23407..0afce99 100644
> --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
> @@ -4,9 +4,13 @@ The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
>  MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
>  electrical signals for DSI.
>  
> +The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
> +in either MIPI-DSI PHY mode or LVDS PHY mode.
> +
>  Required properties:
> -- compatible: Must be:
> +- compatible: Should be one of:
>    - "fsl,imx8mq-mipi-dphy"
> +  - "fsl,imx8qxp-mipi-dphy"
>  - clocks: Must contain an entry for each entry in clock-names.
>  - clock-names: Must contain the following entries:
>    - "phy_ref": phandle and specifier referring to the DPHY ref clock
> @@ -14,6 +18,8 @@ Required properties:
>  - #phy-cells: number of cells in PHY, as defined in
>    Documentation/devicetree/bindings/phy/phy-bindings.txt
>    this must be <0>
> +- fsl,syscon: Phandle to a system controller, as required by the PHY
> +  in i.MX8qxp SoC.
>  
>  Optional properties:
>  - power-domains: phandle to power domain
> -- 
> 2.7.4
>