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Message-ID: <CAEUhbmWVn=W7y+xFGrmpNhQUEqLP-SjKoqeWZ=xgeVaMo5qO=A@mail.gmail.com>
Date: Thu, 10 Dec 2020 21:34:37 +0800
From: Bin Meng <bmeng.cn@...il.com>
To: Yash Shah <yash.shah@...ive.com>
Cc: linux-spi@...r.kernel.org, linux-serial@...r.kernel.org,
linux-pwm@...r.kernel.org, linux-i2c@...r.kernel.org,
linux-kernel <linux-kernel@...r.kernel.org>,
linux-riscv <linux-riscv@...ts.infradead.org>,
devicetree <devicetree@...r.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
broonie@...nel.org,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Albert Ou <aou@...s.berkeley.edu>, lee.jones@...aro.org,
u.kleine-koenig@...gutronix.de,
Thierry Reding <thierry.reding@...il.com>, andrew@...n.ch,
Peter Korsgaard <peter@...sgaard.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Rob Herring <robh+dt@...nel.org>,
Bartosz Golaszewski <bgolaszewski@...libre.com>,
Linus Walleij <linus.walleij@...aro.org>
Subject: Re: [PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to
support SiFive FU740 SoC
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@...ive.com> wrote:
>
> Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
> cores ("harts") that are present on FU740-C000 SoC.
>
> Signed-off-by: Yash Shah <yash.shah@...ive.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Bin Meng <bin.meng@...driver.com>
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