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Message-ID: <mhng-5e629583-5ff4-4523-bfdf-c4254276d95e@palmerdabbelt-glaptop1>
Date:   Fri, 11 Dec 2020 13:41:44 -0800 (PST)
From:   Palmer Dabbelt <palmer@...belt.com>
To:     Linus Torvalds <torvalds@...ux-foundation.org>
CC:         linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [GIT PULL] RISC-V Fixes for 5.10 (unless there's an rc8)

The following changes since commit 30aca1bacb398dec6c1ed5eeca33f355bd7b6203:

  RISC-V: fix barrier() use in <vdso/processor.h> (2020-11-25 09:44:27 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.10-rc8

for you to fetch changes up to ccbbfd1cbf365b38d014351d1482fedd26282041:

  RISC-V: Define get_cycles64() regardless of M-mode (2020-12-10 17:39:43 -0800)

----------------------------------------------------------------
RISC-V Fixes for 5.10 (unless there's an rc8)

I've just got one fix.  It's nothing critical, just a randconfig that
wasn't building.  That said, it does seem pretty safe and is technically
a regression so I'm sending it along for 5.10:

* Define get_cycles64() all the time, as it's used by most
  configurations.

----------------------------------------------------------------
Palmer Dabbelt (1):
      RISC-V: Define get_cycles64() regardless of M-mode

 arch/riscv/include/asm/timex.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

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