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Message-ID: <116ca29a-8270-9b03-520e-bc3ffcf43552@roeck-us.net>
Date: Fri, 11 Dec 2020 15:51:33 -0800
From: Guenter Roeck <linux@...ck-us.net>
To: Kun Yi <kunyi@...gle.com>, jdelvare@...e.com, robh+dt@...nel.org,
mark.rutland@....com, supreeth.venkatesh@....com
Cc: openbmc@...ts.ozlabs.org, linux-hwmon@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH linux hwmon-next v5 3/3] dt-bindings: (hwmon/sbtsi_tmep)
Add SB-TSI hwmon driver bindings
On 12/11/20 1:54 PM, Kun Yi wrote:
> Document device tree bindings for AMD SB-TSI emulated temperature
> sensor.
>
> Signed-off-by: Kun Yi <kunyi@...gle.com>
Any reason for dropping Rob's Reviewed-by: tag ?
Guenter
> ---
> .../devicetree/bindings/hwmon/amd,sbtsi.yaml | 54 +++++++++++++++++++
> 1 file changed, 54 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml
>
> diff --git a/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml b/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml
> new file mode 100644
> index 000000000000..446b09f1ce94
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml
> @@ -0,0 +1,54 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/hwmon/amd,sbtsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: >
> + Sideband interface Temperature Sensor Interface (SB-TSI) compliant
> + AMD SoC temperature device
> +
> +maintainers:
> + - Kun Yi <kunyi@...gle.com>
> + - Supreeth Venkatesh <supreeth.venkatesh@....com>
> +
> +description: |
> + SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
> + interface that reports AMD SoC's Ttcl (normalized temperature),
> + and resembles a typical 8-pin remote temperature sensor's I2C interface
> + to BMC. The emulated thermal sensor can report temperatures in increments
> + of 0.125 degrees, ranging from 0 to 255.875.
> +
> +properties:
> + compatible:
> + enum:
> + - amd,sbtsi
> +
> + reg:
> + maxItems: 1
> + description: |
> + I2C bus address of the device as specified in Section 6.3.1 of the
> + SoC register reference. The SB-TSI address is normally 98h for socket
> + 0 and 90h for socket 1, but it could vary based on hardware address
> + select pins.
> + \[open source SoC register reference\]
> + https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + i2c0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + sbtsi@4c {
> + compatible = "amd,sbtsi";
> + reg = <0x4c>;
> + };
> + };
> +...
>
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