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Date:   Thu, 10 Dec 2020 16:50:55 -0800
From:   Stephen Boyd <>
To:     Doug Anderson <>
Cc:     Roja Rani Yarubandi <>,
        Mark Brown <>,
        Andy Gross <>,
        Bjorn Andersson <>,
        linux-arm-msm <>,
        linux-spi <>,
        LKML <>,
        Akash Asthana <>,
Subject: Re: [PATCH] spi: spi-geni-qcom: Fix NULL pointer access in geni_spi_isr

Quoting Doug Anderson (2020-12-10 15:50:04)
> Hi,
> On Thu, Dec 10, 2020 at 3:32 PM Stephen Boyd <> wrote:
> >
> > Quoting Doug Anderson (2020-12-10 15:07:39)
> > > Hi,
> > >
> > > On Thu, Dec 10, 2020 at 2:58 PM Stephen Boyd <> wrote:
> > > > right? It will only ensure that other irq handlers have completed, which
> > > > may be a problem, but not the only one.
> > > >
> > > > TL;DR: Peek at the irq status register in the timeout logic and skip it
> > > > if the irq is pending?
> > >
> > > I don't have tons of experience with synchronize_irq(), but the
> > > function comment seems to indicate that as long as the interrupt is
> > > pending synchronize_irq() will do what we want even if the CPU that
> > > should handle the interrupt is in an irqsoff section.  Digging a
> > > little bit I guess it relies upon the interrupt controller being able
> > > to read this state, but (hopefully) the GIC can?
> >
> > I didn't read synchronize_irq() more than the single line summary. I
> > thought it would only make sure other irq handlers have finished, which
> > is beside the point of some long section of code that has disabled irqs
> > on CPU0 with local_irq_disable(). And further more, presumably the irq
> > handler could be threaded, and then we could put a sufficiently large
> > msleep() at the start of geni_spi_isr() and see the same problem?
> As I understand it synchronize_irq():
> 1. If the interrupt is not running but is pending at a hardware level,
> it'll wait.
> 2. If the interrupt is currently running it waits for it to finish.
> That should handle all the cases you're talking about including
> waiting for the threaded IRQ handler.  There's an explicit comment
> about the threaded IRQ being accounted for in synchronize_irq():

Ok cool sounds like it would work then. Thanks for reading the code for
me! :)

> > > If it doesn't work like I think it does, I'd be OK with peeking in the
> > > IRQ status register, but we shouldn't _skip_ the logic IMO.  As long
> > > as we believe that an interrupt could happen in the future we
> > > shouldn't return from handle_fifo_timeout().  It's impossible to
> > > reason about how future transfers would work if the pending interrupt
> > > from the previous transfer could fire at any point.
> >
> > Right. I just meant skip the timeout handling logic. We'd have to go
> > back to the timeout and keep waiting until the irq handler can run and
> > complete the completion variable.
> >
> > I forgot that this is half handled in the spi core though. Peeking at
> > m_irq doesn't look very easy to implement. It certainly seems like this
> > means the timeout handler is busted and the diagram earlier could
> > indicate that spi core is driving this logic from
> > spi_transfer_one_message().
> My assumption was that it was still OK (even if not perfect) to still
> process it as a timeout.  I just want to really make sure a future
> interrupt isn't going to show up.

I'm worried about the buffer disappearing if spi core calls handle_err()
but the geni_spi_isr() handler runs both an rx and a cancel/abort
routine. That doesn't seem to be the case though so it looks all fine.

> If we want to try to do better, we can do timeout handling ourselves.
> The SPI core allows for that.
> > So why don't we check for cur_xfer being NULL in the rx/tx handling
> > paths too and bail out there? Does the FIFO need to be cleared out in
> > such a situation that spi core thinks a timeout happened but there's RX
> > data according to m_irq? Do we need to read it all and throw it away? Or
> > does the abort/cancel clear out the RX fifo?
> I don't know for sure, but IMO it's safest to read anything that's in
> the FIFO.  It's also important to adjust the watermark in the TX case.
> The suggestions I provided in my original reply (#2 and #3) handle
> this and are plenty simple.
> As per my original reply, though, anything we do in the ISR doesn't
> replace the changes we need to make to handle_fifo_timeout().  It is
> very important that when handle_fifo_timeout() finishes that no future
> interrupts for old transfers will fire.

Alright. With a proper diagram in the commit text I think doing all of
the points, 1 through 3, would be good and required to leave the
hardware in a sane state for all the scenarios. Why do we need to call
synchronize_irq() at the start and end of handle_fifo_timeout() though?
Presumably having it at the start would make sure the long delayed irq
runs and handles any rx/tx by throwing it away. Sounds great, but having
it at the end leaves me confused. We want to make sure the cancel really
went through?  Don't we know that because the completion variable for
cancel succeeded?

I guess I'm not convinced that the hardware is so bad that it cancels
and aborts the sequencer, raises an irq for that, and then raises an irq
for the earlier rx/tx that the sequencer canceled out. Is that
happening? It's called a sequencer because presumably it runs a sequence
of operations like tx, rx, cs change, cancel, and abort. Hopefully it
doesn't run them out of order. If they run at the same time it's fine,
the irq handler will see all of them and throw away reads, etc.

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