linux-kernel - [irqchip: irq/irqchip-next] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema

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Message-ID: <160769872527.3364.11011368959734662293.tip-bot2@tip-bot2>
Date:   Fri, 11 Dec 2020 14:58:45 -0000
From:   "irqchip-bot for Gregory CLEMENT" <tip-bot2@...utronix.de>
To:     linux-kernel@...r.kernel.org
Cc:     Gregory CLEMENT <gregory.clement@...tlin.com>,
        Marc Zyngier <maz@...nel.org>, Rob Herring <robh@...nel.org>,
        tglx@...utronix.de
Subject: [irqchip: irq/irqchip-next] dt-bindings: interrupt-controller:
 convert icpu intr bindings to json-schema

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     47d5e0b0e1c151c06885a78a108001ead96adc75
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/47d5e0b0e1c151c06885a78a108001ead96adc75
Author:        Gregory CLEMENT <gregory.clement@...tlin.com>
AuthorDate:    Wed, 25 Nov 2020 11:32:01 +01:00
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Fri, 11 Dec 2020 14:47:49 

dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema

Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
Controller to YAML format

Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Reviewed-by: Rob Herring <robh@...nel.org>
Link: https://lore.kernel.org/r/20201125103206.136498-2-gregory.clement@bootlin.com
---
 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt  | 21 ---------------------
 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+), 21 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
deleted file mode 100644
index f5baecc..0000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Microsemi Ocelot SoC ICPU Interrupt Controller
-
-Required properties:
-
-- compatible : should be "mscc,ocelot-icpu-intr"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt source. The value shall be 1.
-- interrupts : Specifies the CPU interrupt the controller is connected to.
-
-Example:
-
-		intc: interrupt-controller@...00070 {
-			compatible = "mscc,ocelot-icpu-intr";
-			reg = <0x70000070 0x70>;
-			#interrupt-cells = <1>;
-			interrupt-controller;
-			interrupt-parent = <&cpuintc>;
-			interrupts = <2>;
-		};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
new file mode 100644
index 0000000..be82920
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microsemi Ocelot SoC ICPU Interrupt Controller
+
+maintainers:
+  - Alexandre Belloni <alexandre.belloni@...tlin.com>
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+  the Microsemi Ocelot interrupt controller that is part of the
+  ICPU. It is connected directly to the MIPS core interrupt
+  controller.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mscc,ocelot-icpu-intr
+
+  '#interrupt-cells':
+    const: 1
+
+  '#address-cells':
+    const: 0
+
+  interrupt-controller: true
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - '#interrupt-cells'
+  - '#address-cells'
+  - interrupt-controller
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    intc: interrupt-controller@...00070 {
+        compatible = "mscc,ocelot-icpu-intr";
+        reg = <0x70000070 0x70>;
+        #interrupt-cells = <1>;
+        #address-cells = <0>;
+        interrupt-controller;
+        interrupt-parent = <&cpuintc>;
+        interrupts = <2>;
+    };
+...