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Message-ID: <20201215160343.GA3935026@robh.at.kernel.org>
Date: Tue, 15 Dec 2020 10:03:43 -0600
From: Rob Herring <robh@...nel.org>
To: Sowjanya Komatineni <skomatineni@...dia.com>
Cc: tudor.ambarus@...rochip.com, p.yadav@...com, robh+dt@...nel.org,
bbrezillon@...nel.org, linux-spi@...r.kernel.org, lukas@...ner.de,
broonie@...nel.org, linux-tegra@...r.kernel.org,
jonathanh@...dia.com, thierry.reding@...il.com,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v3 1/9] dt-bindings: clock: tegra: Add clock ID
TEGRA210_CLK_QSPI_PM
On Fri, 11 Dec 2020 13:15:55 -0800, Sowjanya Komatineni wrote:
> Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
> when using DDR interface mode.
>
> This patch adds clock ID for this to dt-binding.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
> ---
> include/dt-bindings/clock/tegra210-car.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@...nel.org>
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